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| TSC80251G2D 8/16-bit Microcontroller Interfaces 1. Description The TSC80251G2D products are derivatives of the TEMIC Microcontroller family based on the 8/16-bit C251 Architecture. This family of products is tailored to 8/16-bit microcontroller applications requiring an increased instruction throughput, a reduced operating frequency or a larger addressable memory space. The architecture can provide a significant code size reduction when compiling C programs while fully preserving the legacy of C51 assembly routines. The TSC80251G2D derivatives are pin and software compatible with standard 80C51/Fx/Rx/Rx+ with extended on-chip data memory (1 Kbyte RAM) and up to 256 Kbytes of external code and data. Additionally, the TSC83251G2D and TSC87251G2D provide on-chip code memory: 32 Kbytes ROM and 32 Kbytes EPROM/ OTPROM respectively. They provide transparent enhancements to Intel's 8xC251Sx family with an additional Synchronous Serial Link Controller (SSLC supporting I2C, Wire and SPI protocols), a Keyboard interrupt interface, a dedicated Baud Rate Generator for UART, and Power Management features. TSC80251G2D derivatives are optimized for speed and for low power consumption on a wide voltage range. with Serial Communication Note: This Datasheet provides the technical description of the TSC80251G2D derivatives. For further information on the device usage, please request the TSC80251 Programmer's Guide and the TSC80251G1D Design Guide. 2. Typical Applications q q q q q q q ISDN Terminals High-Speed Modems PABX (SOHO) Line Cards DVD ROM and Players Printers Plotters q q q q q q Scanners Banking Machines Barcode Readers Smart Cards Readers High-End Digital Monitors High-End Joysticks Rev. A - May 7, 1999 1 TSC80251G2D 3. Features q Pin and Software Compatibility with Standard 80C51 Products and 80C51Fx/Rx/Rx+ Plug-In Replacement of Intel's 8xC251Sx C251 core: Intel's MCS(R)251 D-step Compliance * 40-byte register file * Registers accessible as Bytes, Words or Dwords * Three-stage instruction pipeline * 16-bit internal code fetch Enriched C51 Instruction Set * 16-bit and 32-bit ALU * Compare and conditional jump instructions * Expanded set of move instructions Linear Addressing 1 Kbyte of On-Chip RAM External Memory Space (Code/Data) Programmable from 64 Kbytes to 256 Kbytes TSC87251G2D: 32 Kbytes of On-Chip EPROM/ OTPROM * SINGLE PULSE Programming Algorithm TSC83251G2D: 32 Kbytes of On-Chip Masked ROM TSC80251G2D: ROMless Version Four 8-bit Parallel I/O Ports (Ports 0, 1, 2 and 3 of the standard 80C51) Serial I/O Port: full duplex UART (80C51 compatible) with independent Baud Rate Generator SSLC: Synchronous Serial Link Controller * I2C multi-master protocol * Wire and SPI master and slave protocols Three 16-bit Timers/Counters (Timers 0, 1 and 2 of the standard 80C51) EWC: Event and Waveform Controller * Compatible with Intel's Programmable Counter Array (PCA) * Common 16-bit timer/counter reference with four possible clock sources (Fosc/4, Fosc/12, Timer 1 and external input) * Five modules, each with four programmable modes: - 16-bit software timer/counter - 16-bit timer/counter capture input and software pulse measurement - High-speed output and 16-bit software pulse width modulation (PWM) - 8-bit hardware PWM without overhead * 16-bit watchdog timer/counter capability q q Secure 14-bit Hardware Watchdog Timer Power Management * Power-On reset (integrated on the chip) * Power-Off flag (cold and warm resets) * Software programmable system clock * Idle mode * Power-Down mode Keyboard Interrupt Interface on Port 1 Non Maskable Interrupt Input (NMI) Real-Time Wait States Inputs (WAIT#/AWAIT#) ONCE mode and full speed Real-Time In-Circuit Emulation support (Third Party Vendors) High Speed Versions: * 4.5 to 5.5 V * 16 MHz and 24 MHz * Typical operating current: 35 mA @ 24 MHz 24 mA @ 16 MHz * Typical power-down current: 2 A Low Voltage Version: * 2.7 to 5.5 V * 16 MHz * Typical operating current: 11 mA @ 3V * Typical power-down current: 1 A Temperature Ranges: * Commercial (0C to +70C) * Industrial (-40C to +85C) * Option: extended range (-55C to +125C) Packages: * PDIL 40, PLCC 44 and VQFP 44 * CDIL 40 and CQPJ 44 with window * Options: known good dice and ceramic packages q q q q q q q q q q q q q q q q q q q q q q 2 Rev. A - May 7, 1999 TSC80251G2D 4. Block Diagram P3(A16) P2(A15-8) P1(A17) P0(AD7-0) PSEN# PORTS 0-3 ALE/PROG# 16-bit Memory Code EA#/VPP 16-bit Memory Address Event and Waveform Controller ROM EPROM OTPROM 32 Kbytes RAM 1 Kbyte Timers 0, 1 and 2 UART Baud Rate Generator AWAIT# Bus Interface Unit Peripheral Interface Unit I2C/SPI/Wire Controller Watchdog Timer 24-bit Program Counter Bus 16-bit Instruction Bus 24-bit Data Address Bus 8-bit Internal Bus RST Power Management XTAL2 Clock Unit Clock System Prescaler 8-bit Data Bus XTAL1 Keyboard Interface CPU Interrupt Handler Unit NMI VDD VSS VSS1 VSS2 Figure 1. TSC80251G2D Block Diagram Rev. A - May 7, 1999 3 TSC80251G2D 5. Pin Description 5.1 Pinout P1.0/T2 P1.1/T2EX P1.2/ECI P1.3/CEX0 P1.4/CEX1/SS# P1.5/CEX2/MISO P1.6/CEX3/SCL/SCK/WAIT# P1.7/A17/CEX4/SDA/MOSI/WCLK RST P3.0/RXD P3.1/TXD P3.2/INT0# P3.3/INT1# P3.4/T0 P3.5/T1 P3.6/WR# P3.7/A16/RD# XTAL2 XTAL1 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VDD P0.0/AD0 P0.1/AD1 P0.2/AD2 P0.3/AD3 P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 EA#/VPP ALE/PROG# PSEN# P2.7/A15 P2.6/A14 P2.5/A13 P2.4/A12 P2.3/A11 P2.2/A10 P2.1/A9 P2.0/A8 TSC80251G2D Figure 2. TSC80251G2D 40-pin DIP package P1.4/CEX1/SS# P1.3/CEX0 P1.2/ECI P1.1/T2EX P1.0/T2 VSS1 VDD P0.0/AD0 P0.1/AD1 P0.2/AD2 P0.3/AD3 P1.5/CEX2/MISO P1.6/CEX3/SCL/SCK/WAIT# P1.7/A17/CEX4/SDA/MOSI/WCLK RST P3.0/RXD AWAIT# P3.1/TXD P3.2/INT0# P3.3/INT1# P3.4/T0 P3.5/T1 6 5 4 3 2 1 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 7 8 9 10 11 12 13 14 15 16 17 TSC80251G2D P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 EA#/VPP NMI ALE/PROG# PSEN# P2.7/A15 P2.6/A14 P2.5/A13 Figure 3. TSC80251G2D 44-pin PLCC Package 4 P3.6/WR# P3.7/A16/RD# XTAL2 XTAL1 VSS VSS2 P2.0/A8 P2.1/A9 P2.2/A10 P2.3/A11 P2.4/A12 18 19 20 21 22 23 24 25 26 27 28 Rev. A - May 7, 1999 TSC80251G2D P1.4/CEX1/SS# P1.3/CEX0 P1.2/ECI P1.1/T2EX P1.0/T2 VSS1 VDD P0.0/AD0 P0.1/AD1 P0.2/AD2 P0.3/AD3 P1.5/CEX2/MISO P1.6/CEX3/SCL/SCK/WAIT# P1.7/A17/CEX4/SDA/MOSI/WCLK RST P3.0/RXD AWAIT# P3.1/TXD P3.2/INT0# P3.3/INT1# P3.4/T0 P3.5/T1 1 2 3 4 5 6 7 8 9 10 11 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 TSC80251G2D P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 EA#/VPP NMI ALE/PROG# PSEN# P2.7/A15 P2.6/A14 P2.5/A13 Figure 4. TSC80251G2D 44-pin VQFP Package Table 1. TSC80251G2D Pin Assignment DIP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 PLCC VQFP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 39 40 41 42 43 44 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Name VSS1 P1.0/T2 P1.1/T2EX P1.2/ECI P1.3/CEX0 P1.4/CEX1/SS# P1.5/CEX2/MISO P1.6/CEX3/SCL/SCK/WAIT# P1.7/A17/CEX4/SDA/MOSI/WCLK RST P3.0/RXD AWAIT# P3.1/TXD P3.2/INT0# P3.3/INT1# P3.4/T0 P3.5/T1 P3.6/WR# P3.7/A16/RD# XTAL2 XTAL1 VSS P3.6/WR# P3.7/A16/RD# XTAL2 XTAL1 VSS VSS2 P2.0/A8 P2.1/A9 P2.2/A10 P2.3/A11 P2.4/A12 12 13 14 15 16 17 18 19 20 21 22 DIP 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 PLCC VQFP 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 VSS2 P2.0/A8 P2.1/A9 P2.2/A10 P2.3/A11 P2.4/A12 P2.5/A13 P2.6/A14 P2.7/A15 PSEN# ALE/PROG# NMI EA#/VPP P0.7/AD7 P0.6/AD6 P0.5/AD5 P0.4/AD4 P0.3/AD3 P0.2/AD2 P0.1/AD1 P0.0/AD0 VDD Name Rev. A - May 7, 1999 5 TSC80251G2D 5.2 Signals Table 2. Product Name Signal Descriptions Signal Name A17 Type O Description Alternate Function 18th Address Bit P1.7 Output to memory as 18th external address bit (A17) in extended bus applications, depending on the values of bits RD0 and RD1 in UCONFIG0 byte (see Table 13, Page 15). 17th Address Bit P3.7 Output to memory as 17th external address bit (A16) in extended bus applications, depending on the values of bits RD0 and RD1 in UCONFIG0 byte (see Table 13, Page 15). Address Lines Upper address lines for the external bus. Address/Data Lines Multiplexed lower address lines and data for the external memory. Address Latch Enable ALE signals the start of an external bus cycle and indicates that valid address information are available on lines A16/A17 and A7:0. An external latch can use ALE to demultiplex the address from address/data bus. Real-time Asynchronous Wait States Input When this pin is active (low level), the memory cycle is stretched until it becomes high. When using the Product Name as a pin-for-pin replacement for a 8xC51 product, AWAIT# can be unconnected without loss of compatibility or power consumption increase (on-chip pull-up). Not available on DIP package. PCA Input/Output pins P1.7:3 CEXx are input signals for the PCA capture mode and output signals for the PCA compare and PWM modes. External Access Enable EA# directs program memory accesses to on-chip or off-chip code memory. For EA#= 0, all program memory accesses are off-chip. For EA#= 1, an access is on-chip ROM if the address is within the range of the on-chip ROM; otherwise the access is off-chip. The value of EA# is latched at reset. For devices without ROM on-chip, EA# must be strapped to ground. PCA External Clock input ECI is the external clock input to the 16-bit PCA timer. P1.2 P2.7:0 P0.7:0 A16 O A15:8(1) AD7:0(1) ALE O I/O O AWAIT# I CEX4:0 I/O EA# I ECI MISO O I/O SPI Master Input Slave Output line P1.5 When SPI is in master mode, MISO receives data from the slave peripheral. When SPI is in slave mode, MISO outputs data to the master controller. SPI Master Output Slave Input line P1.7 When SPI is in master mode, MOSI outputs data to the slave peripheral. When SPI is in slave mode, MOSI receives data from the master controller. External Interrupts 0 and 1 P3.3:2 INT1#/INT0# inputs set IE1:0 in the TCON register. If bits IT1:0 in the TCON register are set, bits IE1:0 are set by a falling edge on INT1#/INT0#. If bits IT1:0 are cleared, bits IE1:0 are set by a low level on INT1#/INT0#. Non Maskable Interrupt Holding this pin high for 24 oscillator periods triggers an interrupt. When using the Product Name as a pin-for-pin replacement for a 8xC51 product, NMI can be unconnected without loss of compatibility or power consumption increase (on-chip pulldown). Not available on DIP package. Port 0 AD7:0 P0 is an 8-bit open-drain bidirectional I/O port. Port 0 pins that have 1s written to them float and can be used as high impedance inputs. To avoid any paraitic current consumption, Floating P0 inputs must be polarized to VDD or VSS. MOSI I/O INT1:0# I NMI I P0.0:7 I/O 6 Rev. A - May 7, 1999 TSC80251G2D Signal Name P1.0:7 Type I/O Description Port 1 P1 is an 8-bit bidirectional I/O port with internal pull-ups. P1 provides interrupt capability for a keyboard interface. Port 2 P2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 P3 is an 8-bit bidirectional I/O port with internal pull-ups. Programming Pulse input The programming pulse is applied to this input for programming the on-chip EPROM/ OTPROM. Program Store Enable/Read signal output PSEN# is asserted for a memory address range that depends on bits RD0 and RD1 in UCONFIG0 byte (see Table 13, Page 15). Alternate Function P2.0:7 P3.0:7 PROG# I/O I/O I A15:8 PSEN# O RD# O Read or 17th Address Bit (A16) P3.7 Read signal output to external data memory depending on the values of bits RD0 and RD1 in UCONFIG0 byte (see Table 13, Page 15). Reset input to the chip Holding this pin high for 64 oscillator periods while the oscillator is running resets the device. The Port pins are driven to their reset conditions when a voltage greater than VIH1 is applied, whether or not the oscillator is running. This pin has an internal pull-down resistor which allows the device to be reset by connecting a capacitor between this pin and VDD. Asserting RST when the chip is in Idle mode or Power-Down mode returns the chip to normal operation. Receive Serial Data P3.0 RXD sends and receives data in serial I/O mode 0 and receives data in serial I/O modes 1, 2 and 3. I2C Serial Clock P1.6 When I2C controller is in master mode, SCL outputs the serial clock to slave peripherals. When I2C controller is in slave mode, SCL receives clock from the master controller. SPI Serial Clock P1.6 When SPI is in master mode, SCK outputs clock to the slave peripheral. When SPI is in slave mode, SCK receives clock from the master controller. I2C Serial Data SDA is the bidirectional I2C data line. SPI Slave Select Input When in Slave mode, SS# enables the slave mode. Timer 1:0 External Clock Inputs When timer 1:0 operates as a counter, a falling edge on the T1:0 pin increments the count. Timer 2 Clock Input/Output P1.0 For the timer 2 capture mode, T2 is the external clock input. For the Timer 2 clock-out mode, T2 is the clock output. Timer 2 External Input P1.1 In timer 2 capture mode, a falling edge initiates a capture of the timer 2 registers. In autoreload mode, a falling edge causes the timer 2 register to be reloaded. In the up-down counter mode, this signal determines the count direction: 1= up, 0= down. Transmit Serial Data P3.1 TXD outputs the shift clock in serial I/O mode 0 and transmits data in serial I/O modes 1, 2 and 3. Digital Supply Voltage Connect this pin to +5V or +3V supply voltage. Programming Supply Voltage The programming supply voltage is applied to this input for programming the on-chip EPROM/ OTPROM. P1.7 P1.4 RST I RXD I/O SCL I/O SCK I/O SDA SS# T1:0 T2 I/O I I/O I/O T2EX I TXD O VDD VPP PWR I Rev. A - May 7, 1999 7 TSC80251G2D Signal Name VSS VSS1 Type GND GND Circuit Ground Connect this pin to ground. Description Alternate Function Secondary Ground 1 This ground is provided to reduce ground bounce and improve power supply bypassing. Connection of this pin to ground is recommended. However, when using the TSC80251G2D as a pin-for-pin replacement for a 8xC51 product, VSS1 can be unconnected without loss of compatibility. Not available on DIP package. Secondary Ground 2 This ground is provided to reduce ground bounce and improve power supply bypassing. Connection of this pin to ground is recommended. However, when using the TSC80251G2D as a pin-for-pin replacement for a 8xC51 product, VSS2 can be unconnected without loss of compatibility. Not available on DIP package. Real-time Synchronous Wait States Input P1.6 The real-time WAIT# input is enabled by setting RTWE bit in WCON (S:A7h). During bus cycles, the external memory system can signal `system ready' to the microcontroller in real time by controlling the WAIT# input signal. Wait Clock Output P1.7 The real-time WCLK output is enabled by setting RTWCE bit in WCON (S:A7h). When enabled, the WCLK output produces a square wave signal with a period of one half the oscillator frequency. Write Write signal output to external memory. Input to the on-chip inverting oscillator amplifier To use the internal oscillator, a crystal/resonator circuit is connected to this pin. If an external oscillator is used, its output is connected to this pin. XTAL1 is the clock source for internal timing. Output of the on-chip inverting oscillator amplifier To use the internal oscillator, a crystal/resonator circuit is connected to this pin. If an external oscillator is used, leave XTAL2 unconnected. P3.6 VSS2 GND WAIT# I WCLK O WR# XTAL1 O I XTAL2 O Note: 1. The description of A15:8/P2.7:0 and AD7:0/P0.7:0 are for the Non-Page mode chip configuration. If the chip is configured in Page mode operation, port 0 carries the lower address bits (A7:0) while port 2 carries the upper address bits (A15:8) and the data (D7:0). 8 Rev. A - May 7, 1999 TSC80251G2D 6. Address Spaces The TSC80251G2D derivatives implement four different address spaces: q q q q On-chip ROM program/code memory (not present in ROMless devices) On-chip RAM data memory Special Function Registers (SFRs) Configuration array 6.1 Program/Code Memory The TSC83251G2D and TSC87251G2D implement 32 Kbytes of on-chip program/code memory. Figure 5 shows the split of the internal and external program/code memory spaces. If EA# is tied to a high level, the 32-Kbyte on-chip program memory is mapped in the lower part of segment FF: where the C251 core jumps after reset. The rest of the program/code memory space is mapped to the external memory. If EA# is tied to a low level, the internal program/code memory is not used and all the accesses are directed to the external memory. The TSC83251G2D products provide the internal program/code memory in a masked ROM memory while the TSC87251G2D products provide it in an EPROM memory. For the TSC80251G2D products, there is no internal program/code memory and EA# must be tied to a low level. Program/code External Memory Space 32 Kbytes FF:8000h FF:7FFFh Program/code Segments FF:FFFFh On-chip ROM/EPROM Code Memory 32 Kbytes EA#= 0 FF:0000h FE:FFFFh EA#= 1 32 Kbytes 64 Kbytes FE:0000h FD:FFFFh Reserved 02:0000h 01:FFFFh 128 Kbytes 01:0000h 00:FFFFh 00:0000h Figure 5. Program/Code Memory Mapping Notes: Special care should be taken when the Program Counter (PC) increments: 1. If the program executes exclusively from on-chip code memory (not from external memory), beware of executing code from the upper eight bytes of the on-chip ROM (FF:7FF8h-FF:7FFFh). Because of its pipeline capability, the TSC80251G2D derivative may attempt to prefetch code from external memory (at an address above FF:7FFFh) and thereby disrupt I/O Ports 0 and 2. Fetching code constants from these 8 bytes does not affect Ports 0 and 2. 2. When PC reaches the end of segment FF:, it loops to the reset address FF:0000h (for compatibility with the C51 Architecture). When PC increments beyond the end of segment FE:, it continues at the reset address FF:0000h (linearity). When PC increments beyond the end of segment 01:, it loops to the beginning of segment 00: (this prevents from its going into the reserved area). Rev. A - May 7, 1999 9 TSC80251G2D 6.2 Data Memory The TSC80251G2D derivatives implement 1 Kbyte of on-chip data RAM. Figure 6 shows the split of the internal and external data memory spaces. This memory is mapped in the data space just over the 32 bytes of registers area (see TSC80251 Programmers' Guide). Hence, the part of the on-chip RAM located from 20h to FFh is bit addressable. This on-chip RAM is not accessible through the program/code memory space. For faster computation with the on-chip ROM/EPROM code of the TSC83251G2D/TSC87251G2D, its upper 16 Kbytes are also mapped in the upper part of the region 00: if the On-Chip Code Memory Map configuration bit is cleared (EMAP# bit in UCONFIG1 byte, see Figure 8). However, if EA# is tied to a low level, the TSC80251G2D derivative is running as a ROMless product and the code is actually fetched in the corresponding external memory (i.e. the upper 16 Kbytes of the lower 32 Kbytes of the segment FF:). If EMAP# bit is set, the on-chip ROM is not accessible through the region 00:. All the accesses to the portion of the data space with no on-chip memory mapped onto are redirected to the external memory. Data External Memory Space 32 Kbytes FF:8000h FF:7FFFh Data Segments FF:FFFFh On-chip ROM/EPROM Code Memory 16 Kbytes EA#= 1 32 Kbytes EA#= 0 FF:0000h FE:FFFFh 16 Kbytes 64 Kbytes FE:0000h FD:FFFFh Reserved 02:0000h 01:FFFFh EMAP#= 0 64 Kbytes 01:0000h 00:FFFFh 00:C000h 00:BFFFh 00:0420h 16 Kbytes 47 Kbytes EMAP#= 1 RAM Data 1 Kbyte 32 bytes reg. Figure 6. Data Memory Mapping 6.3 Special Function Registers The Special Function Registers (SFRs) of the TSC80251G2D derivatives fall into the categories detailed in Table 3 to Table 11. SFRs are placed in a reserved on-chip memory region S: which is not represented in the data memory mapping (Figure 6). The relative addresses within S: of these SFRs are provided together with their reset values in Table 12. They are upward compatible with the SFRs of the standard 80C51 and the Intel's 80C251Sx family. In this table, the C251 core registers are identified by Note 1 and are described in the TSC80251 Programmer's Guide. The other SFRs are described in the TSC80251G1D Design Guide. All the SFRs are bit-addressable using the C251 instruction set. 10 Rev. A - May 7, 1999 TSC80251G2D Table 3. C251 Core SFRs Mnemonic ACC(1) B(1) PSW PSW1 SP(1) Name Accumulator B Register Program Status Word Program Status Word 1 Stack Pointer - LSB of SPX Mnemonic SPH(1) DPL(1) DPH(1) DPXL(1) Name Stack Pointer High - MSB of SPX Data Pointer Low byte - LSB of DPTR Data Pointer High byte - MSB of DPTR Data Pointer Extended Low byte of DPX - Region number Note: 1. These SFRs can also be accessed by their corresponding registers in the register file. Table 4. I/O Port SFRs Mnemonic P0 P1 Name Port 0 Port 1 Mnemonic P2 P3 Name Port 2 Port 3 Table 5. Timers SFRs Mnemonic TL0 TH0 TL1 TH1 TL2 TH2 TCON Name Timer/Counter 0 Low Byte Timer/Counter 0 High Byte Timer/Counter 1 Low Byte Timer/Counter 1 High Byte Timer/Counter 2 Low Byte Timer/Counter 2 High Byte Timer/Counter 0 and 1 Control Mnemonic TMOD T2CON T2MOD RCAP2L RCAP2H WDTRST Name Timer/Counter 0 and 1 Modes Timer/Counter 2 Control Timer/Counter 2 Mode Timer/Counter 2 Reload/Capture Low Byte Timer/Counter 2 Reload/Capture High Byte WatchDog Timer Reset Table 6. Serial I/O Port SFRs Mnemonic SCON SBUF SADEN Name Serial Control Serial Data Buffer Slave Address Mask Mnemonic SADDR BRL BDRCON Name Slave Address Baud Rate Reload Baud Rate Control Table 7. SSLC SFRs Mnemonic SSCON SSDAT SSCS Name Synchronous Serial control Synchronous Serial Data Synchronous Serial Control and Status Mnemonic SSADR SSBR Name Synchronous Serial Address Synchronous Serial Bit Rate Rev. A - May 7, 1999 11 TSC80251G2D Table 8. Event Waveform Control SFRs Mnemonic CCON CMOD CL CH CCAPM0 CCAPM1 CCAPM2 CCAPM3 CCAPM4 Name EWC-PCA Timer/Counter Control EWC-PCA Timer/Counter Mode EWC-PCA Timer/Counter Low Register EWC-PCA Timer/Counter High Register EWC-PCA Timer/Counter Mode 0 EWC-PCA Timer/Counter Mode 1 EWC-PCA Timer/Counter Mode 2 EWC-PCA Timer/Counter Mode 3 EWC-PCA Timer/Counter Mode 4 Mnemonic CCAP0L CCAP1L CCAP2L CCAP3L CCAP4L CCAP0H CCAP1H CCAP2H CCAP3H CCAP4H Name EWC-PCA Compare Capture Module 0 Low Register EWC-PCA Compare Capture Module 1 Low Register EWC-PCA Compare Capture Module 2 Low Register EWC-PCA Compare Capture Module 3 Low Register EWC-PCA Compare Capture Module 4 Low Register EWC-PCA Compare Capture Module 0 High Register EWC-PCA Compare Capture Module 1 High Register EWC-PCA Compare Capture Module 2 High Register EWC-PCA Compare Capture Module 3 High Register EWC-PCA Compare Capture Module 4 High Register Table 9. System Management SFRs Mnemonic PCON POWM Name Power Control Power Management Mnemonic CKRL WCON Name Clock Reload Synchronous Real-Time Wait State Control Table 10. Interrupt SFRs Mnemonic IE0 IE1 IPH0 Name Interrupt Enable Control 0 Interrupt Enable Control 1 Interrupt Priority Control High 0 Mnemonic IPL0 IPH1 IPL1 Name Interrupt Priority Control Low 0 Interrupt Priority Control High 1 Interrupt Priority Control Low 1 Table 11. Keyboard Interface SFRs Mnemonic P1IE P1F Name Port 1 Input Interrupt Enable Port 1 Flag Mnemonic P1LS Name Port 1 Level Selection 12 Rev. A - May 7, 1999 TSC80251G2D Table 12. SFR Addresses and Reset Values 0/8 F8h F0h E8h E0h D8h D0h C8h C0h B8h B0h A8h A0h 98h 90h 88h 80h IPL0 X000 0000 P3 1111 1111 IE0 0000 0000 P2 1111 1111 SCON 0000 0000 P1 1111 1111 TCON 0000 0000 P0 1111 1111 0/8 Reserved Notes: 1. These registers are described in the TSC80251 Programmer's Guide (C251 core registers). 2. In I2C and SPI modes, SSCON is splitted in two separate registers. SSCON reset value is 0000 0000 in I2C mode and 0000 0100 in SPI mode. 3. In read and write modes, SSCS is splitted in two separate registers. SSCS reset value is 1111 1000 in read mode and 0000 0000 in write mode. TMOD 0000 0000 SP(1) 0000 0111 1/9 SBUF XXXX XXXX BRL 0000 0000 SSBR 0000 0000 TL0 0000 0000 DPL(1) 0000 0000 2/A BDRCON XXX0 0000 SSCON (2) 1/9 CH 0000 0000 2/A CCAP0H 0000 0000 3/B CCAP1H 0000 0000 4/C CCAP2H 0000 0000 5/D CCAP3H 0000 0000 6/E CCAP4H 0000 0000 7/F FFh F7h B(1) 0000 0000 CL 0000 0000 ACC(1) 0000 0000 CCON 00X0 0000 PSW(1) 0000 0000 T2CON 0000 0000 CMOD 00XX X000 PSW1(1) 0000 0000 T2MOD XXXX XX00 RCAP2L 0000 0000 RCAP2H 0000 0000 TL2 0000 0000 TH2 0000 0000 CCAPM0 X000 0000 CCAPM1 X000 0000 CCAPM2 X000 0000 CCAPM3 X000 0000 CCAPM4 X000 0000 CCAP0L 0000 0000 CCAP1L 0000 0000 CCAP2L 0000 0000 CCAP3L 0000 0000 CCAP4L 0000 0000 EFh E7h DFh D7h CFh C7h SADEN 0000 0000 IE1 XX0X XXX0 SADDR 0000 0000 IPL1 XX0X XXX0 IPH1 XX0X XXX0 SPH(1) 0000 0000 IPH0 X000 0000 BFh B7h AFh WDTRST 1111 1111 P1LS 0000 0000 SSCS (3) WCON XXXX XX00 A7h 9Fh 97h P1IE 0000 0000 SSDAT 0000 0000 TH1 0000 0000 P1F 0000 0000 SSADR 0000 0000 CKRL 0000 1000 TL1 0000 0000 DPH(1) 0000 0000 3/B TH0 0000 0000 DPXL(1) 0000 0001 4/C POWM 8Fh 0XXX XXXX PCON 0000 0000 87h 5/D 6/E 7/F Rev. A - May 7, 1999 13 TSC80251G2D 6.4 Configuration Bytes The TSC80251G2D derivatives provide user design flexibility by configuring certain operating features at device reset. These features fall into the following categories: * external memory interface (Page mode, address bits, programmed wait states and the address range for RD#, WR#, and PSEN#) * source mode/binary mode opcodes * selection of bytes stored on the stack by an interrupt * mapping of the upper portion of on-chip code memory to region 00: Two user configuration bytes UCONFIG0 (see Figure 7) and UCONFIG1 (see Figure 8) provide the information. When EA# is tied to a low level, the configuration bytes are fetched from the external address space. The TSC80251G2D derivatives reserve the top eight bytes of the memory address space (FF:FFF8h-FF:FFFFh) for an external 8-byte configuration array. Only two bytes are actually used: UCONFIG0 at FF:FFF8h and UCONFIG1 at FF:FFF9h. For the mask ROM devices, configuration information is stored in on-chip memory (see ROM Verifying). When EA# is tied to a high level, the configuration information is retrieved from the on-chip memory instead of the external address space and there is no restriction in the usage of the external memory. UCONFIG0 Configuration Byte 0 7 Bit Number 7 6 WSA1# Bit Mnemonic - 5 WSA0# 4 XALE# 3 RD1 2 RD0 Description 1 PAGE# 0 SRC Reserved Set this bit when writing to UCONFIG0. Wait State A bits Select the number of wait states for RD#, WR# and PSEN# signals for external memory accesses (all regions except 01:). WSA1# WSA0# Number of Wait States 0 0 3 0 1 2 1 0 1 1 1 0 Extend ALE bit Clear to extend the duration of the ALE pulse from TOSC to 3*TOSC. Set to minimize the duration of the ALE pulse to 1*TOSC. Memory Signal Select bits Specify a 18-bit, 17-bit or 16-bit external address bus and the usage of RD#, WR# and PSEN# signals (see Table 13). Page Mode Select bit(1) Clear to select the faster Page mode with A15:8/D7:0 on Port 2 and A7:0 on Port 0. Set to select the non-Page mode(2) with A15:8 on Port 2 and A7:0/D7:0 on Port 0. Source Mode/Binary Mode Select bit Clear to select the binary mode. Set to select the source mode. 6 WSA1# 5 WSA0# 4 3 2 1 XALE# RD1 RD0 PAGE# 0 SRC Notes: 1. UCONFIG0 is fetched twice so it can be properly read both in Page or Non-Page modes. If P2.1 is cleared during the first data fetch, a Page mode configuration is used, otherwise the subsequent fetches are performed in Non-Page mode. 2. This selection provides compatibility with the standard 80C51 hardware which is multiplexing the address LSB and the data on Port 0. Figure 7. Configuration Byte 0 14 Rev. A - May 7, 1999 TSC80251G2D UCONFIG1 Configuration Byte 1 7 CSIZE Bit Number 6 Bit Mnemonic CSIZE TSC87251G2D 7 TSC80251G2D TSC83251G2D bit(1) 5 - 4 INTR 3 WSB 2 WSB1# Description 1 WSB0# 0 EMAP# On-Chip Code Memory Size Clear to select 16 Kbytes of on-chip code memory (TSC87251G1D product). Set to select 32 Kbytes of on-chip code memory (TSC87251G2D product). Reserved Set this bit when writing to UCONFIG1. Reserved Set this bit when writing to UCONFIG1. Reserved Set this bit when writing to UCONFIG1. Interrupt Mode bit(2) Clear so that the interrupts push two bytes onto the stack (the two lower bytes of the PC register). Set so that the interrupts push four bytes onto the stack (the three bytes of the PC register and the PSW1 register). Wait State B bit(3) Clear to generate one wait state for memory region 01:. Set for no wait states for memory region 01:. Wait State B bits Select the number of wait states for RD#, WR# and PSEN# signals for external memory accesses (only region 01:). WSB1# WSB0# Number of Wait States 0 0 3 0 1 2 1 0 1 1 1 0 On-Chip Code Memory Map bit Clear to map the upper 16 Kbytes of on-chip code memory (at FF:4000h-FF:7FFFh) to the data space (at 00:C000h-00:FFFFh). Set not to map the upper 16 Kbytes of on-chip code memory (at FF:4000h-FF:7FFFh) to the data space. 6 5 4 INTR 3 WSB 2 WSB1# 1 WSB0# 0 EMAP# Notes: 1. The CSIZE is only available on EPROM/OTPROM products. 2. Two or four bytes are transparently popped according to INTR when using the RETI instruction. INTR must be set if interrupts are used with code executing outside region FF:. 3. Use only for Step A compatibility; set this bit when WSB1:0# are used. Figure 8. Configuration Byte 1 Table 13. Address Ranges and Usage of RD#, WR# and PSEN# Signals RD1 0 0 1 1 RD0 0 1 0 1 P1.7 A17 I/O pin I/O pin I/O pin P3.7/RD# A16 A16 I/O pin Read signal for regions 00: and 01: PSEN# Read signal for all external memory locations Read signal for all external memory locations Read signal for all external memory locations Read signal for regions FE: and FF: WR# Write signal for all external memory locations Write signal for all external memory locations Write signal for all external memory locations Write signal for all external memory locations External Memory 256 Kbytes 128 Kbytes 64 Kbytes 2 x 64 Kbytes(1) Note: 1. This selection provides compatibility with the standard 80C51 hardware which has separate external memory spaces for data and code. Rev. A - May 7, 1999 15 TSC80251G2D 7. Instruction Set Summary This section contains tables that summarize the instruction set. For each instruction there is a short description, its length in bytes, and its execution time in states (one state time is equal to two system clock cycles). There are two concurrent processes limiting the effective instruction throughput: q q Instruction Fetch Instruction Execution Table 20 to Table 34 assume code executing from on-chip memory, then the CPU is fetching 16-bit at a time and this is never limiting the execution speed. If the code is fetched from external memory, a pre-fetch queue will store instructions ahead of execution to optimize the memory bandwidth usage when slower instructions are executed. However, the effective speed may be limited depending on the average size of instructions (for the considered section of the program flow). The maximum average instruction throughput is provided by Table 14 depending on the external memory configuration (from Page Mode to Non-Page Mode and the maximum number of wait states). If the average size of instructions is not an integer, the maximum effective throughput is found by pondering the number of states for the neighbor integer values. Table 14. Minimum Number of States per Instruction for given Average Sizes Average size of Instructions (bytes) 1 2 3 4 5 Page Mode (states) 1 2 3 4 5 Non-Page Mode (states) 0 Wait State 2 4 6 8 10 1 Wait State 3 6 9 12 15 2 Wait States 4 8 12 16 20 3 Wait States 5 10 15 20 25 4 Wait States 6 12 18 24 30 If the average execution time of the considered instructions is larger than the number of states given by Table 14, this larger value will prevail as the limiting factor. Otherwise, the value from Table 14 must be taken. This is providing a fair estimation of the execution speed but only the actual code execution can provide the final value. 7.1 Notation for Instruction Operands Table 15 to Table 19 provide notation for Instruction Operands. Table 15. Notation for Direct Addressing Direct Address dir8 dir16 Description A direct 8-bit address. This can be a memory address (00h-7Fh) or a SFR address (80hFFh). It is a byte (default), word or double word depending on the other operand. A 16-bit memory address (00:0000h-00:FFFFh) used in direct addressing. C251 C51 Table 16. Notation for Immediate Addressing Immediate Address #data #data16 #0data16 #1data16 #short Description An 8-bit constant that is immediately addressed in an instruction A 16-bit constant that is immediately addressed in an instruction A 32-bit constant that is immediately addressed in an instruction. The upper word is filled with zeros (#0data16) or ones (#1data16). A constant, equal to 1, 2, or 4, that is immediately addressed in an instruction. C251 C51 Rev. A - May 7, 1999 16 TSC80251G2D Table 17. Notation for Bit Addressing Direct Address bit51 bit Description A directly addressed bit (bit number= 00h-FFh) in memory or an SFR. Bits 00h-7Fh are the 128 bits in byte locations 20h-2Fh in the on-chip RAM. Bits 80h-FFh are the 128 bits in the 16 SFRs with addresses that end in 0h or 8h, S:80h, S:88h, S:90h,..., S:F0h, S:F8h. A directly addressed bit in memory locations 00:0020h-00:007Fh or in any defined SFR. C251 C51 Table 18. Notation for Destination in Control Instructions Direct Address rel addr11 addr16 addr24 Description A signed (two's complement) 8-bit relative address. The destination is -128 to +127 bytes relative to the next instruction's first byte. An 11-bit target address. The target is in the same 2-Kbyte block of memory as the next instruction's first byte. A 16-bit target address. The target can be anywhere within the same 64-Kbyte region as the next instruction's first byte. A 24-bit target address. The target can be anywhere within the 16-Mbyte address space. C251 C51 Table 19. Notation for Register Operands Register @Ri Rn n Rm Rmd Rms m, md, ms WRj WRjd WRjs @WRj @WRj +dis16 j, jd, js DRk DRkd DRks @DRk @DRk +dis16 k, kd, ks Description A memory location (00h-FFh) addressed indirectly via byte registers R0 or R1 Byte register R0-R7 of the currently selected register bank Byte register index: n= 0-7 Byte register R0-R15 of the currently selected register file Destination register Source register Byte register index: m, md, ms= 0-15 Word register WR0, WR2, ..., WR30 of the currently selected register file Destination register Source register A memory location (00:0000h-00:FFFFh) addressed indirectly through word register WR0WR30, is the target address for jump instructions. A memory location (00:0000h-00:FFFFh) addressed indirectly through word register (WR0WR30) + 16-bit signed (two's complement) displacement value Word register index: j, jd, js= 0-30 Dword register DR0, DR4, ..., DR28, DR56, DR60 of the currently selected register file Destination register Source register A memory location (00:0000h-FF:FFFFh) addressed indirectly through dword register DR0DR28, DR56 and DR60, is the target address for jump instruction A memory location (00:0000h-FF:FFFFh) addressed indirectly through dword register (DR0DR28, DR56, DR60) + 16-bit (two's complement) signed displacement value Dword register index: k, kd, ks= 0, 4, 8..., 28, 56, 60 C251 C51 17 Rev. A - May 7, 1999 TSC80251G2D 7.2 Size and Execution Time for Instruction Families Table 20. Summary of Add and Subtract Instructions Add Subtract Add with Carry Subtract with Borrow ADD Mnemonic A, Rn Register to ACC Binary Mode Comments Bytes 1 2 1 2 3 3 3 4 5 5 4 4 5 5 4 4 1 2 1 2 Source Mode Bytes 2 2 2 2 2 2 2 3 4 4 3 3 4 4 3 3 2 2 2 2 States 1 1(2) 2 1 2 3 5 3 4 6 3(2) 4 3(3) 4(4) 3(3) 4(3) 1 1(2) 2 1 States 2 1(2) 3 1 1 2 4 2 3 5 2(2) 3 2(3) 3(4) 2(3) 3(3) 2 1(2) 3 1 ADD A, dir8 A, @Ri A, #data Rmd, Rms WRjd, WRjs DRkd, DRks Rm, #data WRj, #data16 Direct address to ACC Indirect address to ACC Immediate data to ACC Byte register to/from byte register Word register to/from word register Dword register to/from dword register Immediate 8-bit data to/from byte register Immediate 16-bit data to/from word register 16-bit unsigned immediate data to/from dword register Direct address (on-chip RAM or SFR) to/from byte register Direct address (on-chip RAM or SFR) to/from word register Direct address (64K) to/from byte register Direct address (64K) to/from word register Indirect address (64K) to/from byte register Indirect address (16M) to/from byte register Register to/from ACC with carry Direct address (on-chip RAM or SFR) to/from ACC with carry Indirect address to/from ACC with carry Immediate data to/from ACC with carry ADD / SUB DRk, #0data16 Rm, dir8 WRj, dir8 Rm, dir16 WRj, dir16 Rm, @WRj Rm, @DRk A, Rn ADDC / SUBB A, dir8 A, @Ri A, #data Notes: 1. A shaded cell denotes an instruction in the C51 Architecture. 2. If this instruction addresses an I/O Port (Px, x= 0-3), add 1 to the number of states. Add 2 if it addresses a Peripheral SFR. 3. If this instruction addresses external memory location, add N+2 to the number of states (N: number of wait states). 4. If this instruction addresses external memory location, add 2(N+2) to the number of states (N: number of wait states). Rev. A - May 7, 1999 18 TSC80251G2D Table 21. Summary of Increment and Decrement Instructions Increment Increment Decrement Decrement INC Mnemonic A ACC by 1 Register by 1 Binary Mode Comments Bytes 1 1 2 1 3 3 3 3 1 Source Mode Bytes 1 2 2 2 2 2 2 2 1 States 1 1 2(2) 3 2 2 4 5 1 States 1 2 2(2) 4 1 1 3 4 1 INC DEC Rn dir8 @Ri Direct address (on-chip RAM or SFR) by 1 Indirect address by 1 Byte register by 1, 2, or 4 Word register by 1, 2, or 4 Double word register by 1, 2, or 4 Double word register by 1, 2, or 4 Data pointer by 1 INC DEC INC DEC INC Rm, #short WRj, #short DRk, #short DRk, #short DPTR Notes: 1. A shaded cell denotes an instruction in the C51 Architecture. 2. If this instruction addresses an I/O Port (Px, x= 0-3), add 2 to the number of states. Add 3 if it addresses a Peripheral SFR. Table 22. Summary of Compare Instructions Compare CMP Mnemonic Rmd, Rms WRjd, WRjs DRkd, DRks Rm, #data WRj, #data16 DRk, #0data16 Register with register Binary Mode Comments Bytes 3 3 3 4 5 5 5 4 4 5 5 4 4 Word register with word register Dword register with dword register Register with immediate data Word register with immediate 16-bit data Dword register with zero-extended 16-bit immediate data Dword register with one-extended 16-bit immediate data Direct address (on-chip RAM or SFR) with byte register Direct address (on-chip RAM or SFR) with word register Direct address (64K) with byte register Direct address (64K) with word register Indirect address (64K) with byte register Indirect address (16M) with byte register Source Mode Bytes 2 2 2 3 4 4 4 3 3 4 4 3 3 States 2 3 5 3 4 6 6 3(1) 4 3(2) 4(3) 3(2) 4(2) States 1 2 4 2 3 5 5 2(1) 3 2(2) 3(3) 2(2) 3(2) CMP DRk, #1data16 Rm, dir8 WRj, dir8 Rm, dir16 WRj, dir16 Rm, @WRj Rm, @DRk Notes: 1. If this instruction addresses an I/O Port (Px, x= 0-3), add 1 to the number of states. Add 2 if it addresses a Peripheral SFR. 2. If this instruction addresses external memory location, add N+2 to the number of states (N: number of wait states). 3. If this instruction addresses external memory location, add 2(N+2) to the number of states (N: number of wait states). 19 Rev. A - May 7, 1999 TSC80251G2D Table 23. Summary of Logical Instructions (1/2) Logical AND(1) Logical OR(1) Logical Exclusive OR(1) Clear(1) Complement(1) Rotate Left Rotate Left Carry ANL Rotate Right Rotate Right Carry RR A RRC A Mnemonic A, Rn A, dir8 A, @Ri A, #data dir8, A dir8, #data Rmd, Rms register to ACC Binary Mode Comments Bytes 1 2 1 2 2 3 3 3 4 5 4 4 5 5 4 4 1 1 1 1 1 1 Direct address (on-chip RAM or SFR) to ACC Indirect address to ACC Immediate data to ACC ACC to direct address Immediate 8-bit data to direct address Byte register to byte register Word register to word register Immediate 8-bit data to byte register Immediate 16-bit data to word register Direct address (on-chip RAM or SFR) to byte register Direct address (on-chip RAM or SFR) to word register Direct address (64K) to byte register Direct address (64K) to word register Indirect address (64K) to byte register Indirect address (16M) to byte register Clear ACC Complement ACC Rotate ACC left Rotate ACC left through CY Rotate ACC right Rotate ACC right through CY Source Mode Bytes 2 2 2 2 2 3 2 2 3 4 3 3 4 4 3 3 1 1 1 1 1 1 States 1 1(3) 2 1 2(4) 3(4) 2 3 3 4 3(3) 4 3(5) 4(6) 3(5) 4(5) 1 1 1 1 1 1 States 2 1(3) 3 1 2(4) 3(4) 1 2 2 3 2(3) 3 2(5) 3(6) 2(5) 3(5) 1 1 1 1 1 1 ANL ORL XRL WRjd, WRjs Rm, #data WRj, #data16 Rm, dir8 WRj, dir8 Rm, dir16 WRj, dir16 Rm, @WRj Rm, @DRk CLR CPL RL RLC RR RRC A A A A A A Notes: 1. Logical instructions that affect a bit are in Table 29. 2. A shaded cell denotes an instruction in the C51 Architecture. 3. If this instruction addresses an I/O Port (Px, x= 0-3), add 1 to the number of states. Add 2 if it addresses a Peripheral SFR. 4. If this instruction addresses an I/O Port (Px, x= 0-3), add 2 to the number of states. Add 3 if it addresses a Peripheral SFR. 5. If this instruction addresses external memory location, add N+2 to the number of states (N: number of wait states). 6. If this instruction addresses external memory location, add 2(N+2) to the number of states (N: number of wait states). Rev. A - May 7, 1999 20 TSC80251G2D Table 24. Summary of Logical Instructions (2/2) Shift Left Logical SLL Shift Right Arithmetic SRA Shift Right Logical SRL Swap SWAP A Mnemonic Rm WRj Rm WRj Rm WRj A Binary Mode Comments Bytes States 2 2 2 2 2 2 2 Source Mode Bytes 2 2 2 2 2 2 1 States 1 1 1 1 1 1 2 SLL Shift byte register left through the MSB Shift word register left through the MSB Shift byte register right Shift word register right Shift byte register left Shift word register left Swap nibbles within ACC 3 3 3 3 3 3 1 SRA SRL SWAP Note: 1. A shaded cell denotes an instruction in the C51 Architecture. Table 25. Summary of Multiply, Divide and Decimal-adjust Instructions Multiply Divide Divide Decimal-adjust ACC for Addition (BCD) MUL AB MUL Mnemonic AB Multiply A and B Binary Mode Comments Bytes 1 3 3 1 3 3 1 Source Mode Bytes 1 2 2 1 2 2 1 States 5 6 12 10 11 21 1 States 5 5 11 10 10 20 1 MUL Rmd, Rms WRjd, WRjs AB Multiply byte register and byte register Multiply word register and word register Divide A and B Divide byte register and byte register Divide word register and word register Decimal adjust ACC DIV Rmd, Rms WRjd, WRjs DA A Note: 1. A shaded cell denotes an instruction in the C51 Architecture. 21 Rev. A - May 7, 1999 TSC80251G2D Table 26. Summary of Move Instructions (1/3) Move Move Move Move Move to High word with Sign extension with Zero extension Code eXtended MOVH Mnemonic MOVH MOVS MOVZ MOVC DRk, #data16 WRj, Rm WRj, Rm A, @A +DPTR A, @A +PC A, @Ri Binary Mode Comments Bytes 16-bit immediate data into upper word of dword register Byte register to word register with sign extension Byte register to word register with zeros extension Code byte relative to DPTR to ACC Code byte relative to PC to ACC Extended memory (8-bit address) to ACC(2) Extended memory (16-bit address) to ACC(2) ACC to extended memory (8-bit address)(2) ACC to extended memory (16-bit address)(2) 5 3 3 1 1 1 1 1 1 Source Mode Bytes 4 2 2 1 1 1 1 1 1 States 3 2 2 6(3) 6(3) 4 3(4) 4 4(3) States 2 1 1 6(3) 6(3) 5 3(4) 4 4(3) MOVX A, @DPTR @Ri, A @DPTR, A Notes: 1. A shaded cell denotes an instruction in the C51 Architecture. 2. Extended memory addressed is in the region specified by DPXL (reset value= 01h). 3. If this instruction addresses external memory location, add N+1 to the number of states (N: number of wait states). 4. If this instruction addresses external memory location, add N+2 to the number of states (N: number of wait states). Table 27. Summary of Move Instructions (2/3) Move(1) MOV Mnemonic A, Rn A, dir8 A, @Ri A, #data Rn, A Rn, dir8 Rn, #data Register to ACC Binary Mode Comments Bytes 1 2 1 2 1 2 2 2 2 3 2 3 1 2 2 3 Direct address (on-chip RAM or SFR) to ACC Indirect address to ACC Immediate data to ACC ACC to register Direct address (on-chip RAM or SFR) to register Immediate data to register ACC to direct address (on-chip RAM or SFR) Register to direct address (on-chip RAM or SFR) Direct address to direct address (on-chip RAM or SFR) Indirect address to direct address (on-chip RAM or SFR) Immediate data to direct address (on-chip RAM or SFR) ACC to indirect address Direct address (on-chip RAM or SFR) to indirect address Immediate data to indirect address Load Data Pointer with a 16-bit constant Source Mode Bytes 2 2 2 2 2 3 3 2 3 3 3 3 2 3 3 3 States 1 1(3) 2 1 1 1(3) 1 2(3) 2(3) 3(4) 3(3) 3(3) 3 3(3) 3 2 States 2 1(3) 3 1 2 2(3) 2 2(3) 3(3) 3(4) 4(3) 3(3) 4 4(3) 4 2 MOV dir8, A dir8, Rn dir8, dir8 dir8, @Ri dir8, #data @Ri, A @Ri, dir8 @Ri, #data DPTR, #data16 Notes: 1. Instructions that move bits are in Table 29. 2. Move instructions from the C51 Architecture. 3. If this instruction addresses an I/O Port (Px, x= 0-3), add 1 to the number of states. Add 2 if it addresses a Peripheral SFR. 4. Apply note 3 for each dir8 operand. Rev. A - May 7, 1999 22 TSC80251G2D Table 28. Summary of Move Instructions (3/3) Move(1) MOV Mnemonic Rmd, Rms WRjd, WRjs DRkd, DRks Rm, #data WRj, #data16 DRk, #0data16 DRk, #1data16 Rm, dir8 WRj, dir8 DRk, dir8 Rm, dir16 WRj, dir16 DRk, dir16 Rm, @WRj Rm, @DRk WRjd, @WRjs WRj, @DRk Binary Mode Comments Bytes Byte register to byte register Word register to word register Dword register to dword register Immediate 8-bit data to byte register Immediate 16-bit data to word register zero-ext 16bit immediate data to dword register one-ext 16bit immediate data to dword register Direct address (on-chip RAM or SFR) to byte register Direct address (on-chip RAM or SFR) to word register Direct address (on-chip RAM or SFR) to dword register Direct address (64K) to byte register Direct address (64K) to word register Direct address (64K) to dword register Indirect address (64K) to byte register Indirect address (16M) to byte register Indirect address (64K) to word register Indirect address (16M) to word register Byte register to direct address (on-chip RAM or SFR) Word register to direct address (on-chip RAM or SFR) Dword register to direct address (on-chip RAM or SFR) Byte register to direct address (64K) Word register to direct address (64K) Dword register to direct address (64K) Byte register to indirect address (64K) Byte register to indirect address (16M) Word register to indirect address (64K) Word register to indirect address (16M) Indirect with 16-bit displacement (64K) to byte register 3 3 3 4 5 5 5 4 4 4 5 5 5 4 4 4 4 4 4 4 5 5 5 4 4 4 4 5 5 5 5 5 5 5 5 Source Mode Bytes 2 2 2 3 4 4 4 3 3 3 4 4 4 3 3 3 3 3 3 3 4 4 4 3 3 3 3 4 4 4 4 4 4 4 4 States 2 2 3 3 3 5 5 3(3) 4 6 3 (4) (5) States 1 1 2 2 2 4 4 2(3) 3 5 2(4) 3(5) 5(6) 2(4) 3(4) 3(5) 4(5) 3(3) 4 6 3(4) 4(5) 6(6) 3(4) 4(4) 4(5) 5(5) 5(4) 6(5) 6(4) 7(5) 5(4) 6(5) 6(4) 7(5) 4 6(6) 3 (4) 4(4) 4 (5) 5(5) 4 (3) MOV dir8, Rm dir8, WRj dir8, DRk dir16, Rm dir16, WRj dir16, DRk @WRj, Rm @DRk, Rm @WRjd, WRjs @DRk, WRj Rm, @WRj +dis16 5 7 4 (4) (5) 5 7(6) 4 (4) 5(4) 5 (5) 6(5) 6(4) 7(5) 7(4) 8(5) 6(4) 7(5) 7(4) 8(5) WRj, @WRj +dis16 Indirect with 16-bit displacement (64K) to word register Rm, @DRk +dis24 Indirect with 16-bit displacement (16M) to byte register WRj, @WRj +dis24 Indirect with 16-bit displacement (16M) to word register @WRj +dis16, Rm Byte register to indirect with 16-bit displacement (64K) @WRj +dis16, WRj Word register to indirect with 16-bit displacement (64K) @DRk +dis24, Rm Byte register to indirect with 16-bit displacement (16M) @DRk +dis24, WRj Word register to indirect with 16-bit displacement (16M) Notes: 1. Instructions that move bits are in Table 29. 2. Move instructions unique to the C251 Architecture. 3. If this instruction addresses an I/O Port (Px, x= 0-3), add 1 to the number of states. Add 2 if it addresses a Peripheral SFR. 4. If this instruction addresses external memory location, add N+2 to the number of states (N: number of wait states). 5. If this instruction addresses external memory location, add 2(N+1) to the number of states (N: number of wait states). 6. If this instruction addresses external memory location, add 4(N+2) to the number of states (N: number of wait states). 23 Rev. A - May 7, 1999 TSC80251G2D Table 29. Summary of Bit Instructions Clear Bit Set Bit Complement Bit AND Carry with Bit AND Carry with Complement of Bit OR Carry with Bit OR Carry with Complement of Bit Move Bit to Carry Move Bit from Carry CLR Mnemonic CY Clear carry Clear direct bit Clear direct bit Set carry Set direct bit Set direct bit Complement carry Complement direct bit Complement direct bit And direct bit to carry And direct bit to carry Binary Mode Comments Bytes 1 2 4 1 2 4 1 2 4 2 4 2 4 2 4 2 4 2 4 2 4 Source Mode Bytes 1 2 3 1 2 3 1 2 3 2 3 2 3 2 3 2 3 2 3 2 3 States 1 2(3) 4(3) 1 2(3) 4(3) 1 2(3) 4(3) 1(2) 3(2) 1(2) 3(2) 1(2) 3(2) 1(2) 3(2) 1(2) 3(2) 2(3) 4(3) States 1 2(3) 3(3) 1 2(3) 3(3) 1 2(3) 3(3) 1(2) 2(2) 1(2) 2(2) 1(2) 2(2) 1(2) 2(2) 1(2) 2(2) 2(3) 3(3) CLR bit51 bit CY SETB bit51 bit CY CPL bit51 bit CY, bit51 ANL CY, bit CY, /bit51 CY, /bit CY, bit51 And complemented direct bit to carry And complemented direct bit to carry Or direct bit to carry Or direct bit to carry Or complemented direct bit to carry Or complemented direct bit to carry Move direct bit to carry Move direct bit to carry Move carry to direct bit Move carry to direct bit ORL CY, bit CY, /bit51 CY, /bit CY, bit51 MOV CY, bit bit51, CY bit, CY Notes: 1. A shaded cell denotes an instruction in the C51 Architecture. 2. If this instruction addresses an I/O Port (Px, x= 0-3), add 1 to the number of states. Add 2 if it addresses a Peripheral SFR. 3. If this instruction addresses an I/O Port (Px, x= 0-3), add 2 to the number of states. Add 3 if it addresses a Peripheral SFR. Rev. A - May 7, 1999 24 TSC80251G2D Table 30. Summary of Exchange, Push and Pop Instructions Exchange bytes Exchange Digit Push Pop XCH A, Mnemonic A, Rn ACC and register Binary Mode Comments Bytes 1 2 1 1 2 4 5 3 3 3 2 3 3 3 Source Mode Bytes 2 2 2 2 2 3 4 2 2 2 2 2 2 2 States 3 3 (3) States 4 3(3) 5 5 2(2) 3 5 3 4 8 3(2) 2 4 8 XCH A, dir8 A, @Ri ACC and direct address (on-chip RAM or SFR) ACC and indirect address ACC low nibble and indirect address (256 bytes) Push direct address onto stack Push immediate data onto stack Push 16-bit immediate data onto stack Push byte register onto stack Push word register onto stack Push double word register onto stack Pop direct address (on-chip RAM or SFR) from stack Pop byte register from stack Pop word register from stack Pop double word register from stack 4 4 2(2) 4 5 4 5 9 3(2) 3 5 9 XCHD A, @Ri dir8 #data PUSH #data16 Rm WRj DRk dir8 POP Rm WRj DRk Notes: 1. A shaded cell denotes an instruction in the C51 Architecture. 2. If this instruction addresses an I/O Port (Px, x= 0-3), add 1 to the number of states. Add 2 if it addresses a Peripheral SFR. 3. If this instruction addresses an I/O Port (Px, x= 0-3), add 2 to the number of states. Add 3 if it addresses a Peripheral SFR. Table 31. Summary of Conditional Jump Instructions (1/2) Jump conditional on status Jcc rel (PC) (PC) + size (instr); IF [cc] THEN (PC) (PC) + rel Mnemonic JC JNC JE JNE JG JLE JSL JSLE JSG JSGE rel rel rel rel rel rel rel rel rel rel Jump if carry Jump if not carry Jump if equal Jump if not equal Jump if greater than Binary Mode Comments Bytes 2 2 3 3 3 3 3 3 3 3 Source Mode Bytes 2 2 2 2 2 2 2 2 2 2 States 1/4(3) 1/4(3) 2/5(3) 2/5(3) 2/5(3) 2/5(3) 2/5(3) 2/5(3) 2/5(3) 2/5(3) States 1/4(3) 1/4(3) 1/4(3) 1/4(3) 1/4(3) 1/4(3) 1/4(3) 1/4(3) 1/4(3) 1/4(3) Jump if less than, or equal Jump if less than (signed) Jump if less than, or equal (signed) Jump if greater than (signed) Jump if greater than or equal (signed) Notes: 1. A shaded cell denotes an instruction in the C51 Architecture. 2. States are given as jump not-taken/taken. 3. In internal execution only, add 1 to the number of states of the `jump taken' if the destination address is internal and odd. 25 Rev. A - May 7, 1999 TSC80251G2D Table 32. Summary of Conditional Jump Instructions (2/2) Jump if bit Jump if not bit Jump if bit and clear JB Jump if accumulator is zero Jump if accumulator is not zero Compare and jump if not equal JZ rel JNZ rel CJNE Decrement and jump if not zero DJNZ Mnemonic bit51, rel bit, rel bit51, rel bit, rel bit51, rel bit, rel rel rel A, dir8, rel Binary Mode(2) Comments Bytes States 2/5(3)(6) 4/7(3)(6) 2/5(3)(6) 4/7(3)(6) 4/7(5)(6) 7/10(5)(6) 2/5(6) 2/5(6) 2/5(3)(6) 2/5(6) 2/5(6) 3/6(6) 2/5(6) 3/6(4)(6) Source Mode(2) Bytes 3 4 3 4 3 4 2 2 3 3 4 4 3 3 States 2/5(3)(6) 3/6(3)(6) 2/5(3)(6) 3/6(3) 4/7(5)(6) 6/9(5)(6) 2/5(6) 2/5(6) 2/5(3)(6) 2/5(6) 3/6(6) 4/7(6) 3/6(6) 3/6(4)(6) JB Jump if direct bit is set Jump if direct bit of 8-bit address location is set Jump if direct bit is not set Jump if direct bit of 8-bit address location is not set Jump if direct bit is set & clear bit Jump if direct bit of 8-bit address location is set and clear Jump if ACC is zero Jump if ACC is not zero Compare direct address to ACC and jump if not equal Compare immediate to ACC and jump if not equal Compare immediate to register and jump if not equal Compare immediate to indirect and jump if not equal Decrement register and jump if not zero Decrement direct address and jump if not zero 3 5 3 5 3 5 2 2 3 3 3 3 2 3 JNB JBC JZ JNZ CJNE A, #data, rel Rn, #data, rel @Ri, #data, rel DJNZ Rn, rel dir8, rel Notes: 1. A shaded cell denotes an instruction in the C51 Architecture. 2. States are given as jump not-taken/taken. 3. If this instruction addresses an I/O Port (Px, x= 0-3), add 1 to 4. If this instruction addresses an I/O Port (Px, x= 0-3), add 2 to 5. If this instruction addresses an I/O Port (Px, x= 0-3), add 3 to 6. In internal execution only, add 1 to the number of states of the the number of states. Add 2 if the number of states. Add 3 if the number of states. Add 5 if `jump taken' if the destination it addresses a Peripheral SFR. it addresses a Peripheral SFR. it addresses a Peripheral SFR. address is internal and odd. Rev. A - May 7, 1999 26 TSC80251G2D Table 33. Summary of unconditional Jump Instructions Absolute jump Extended jump Long jump Short jump Jump indirect No operation AJMP Mnemonic AJMP EJMP addr11 addr24 @DRk @WRj addr16 rel @A +DPTR Absolute jump Extended jump Binary Mode Comments Bytes 2 5 3 3 3 2 1 1 Source Mode Bytes 2 4 2 2 3 2 1 1 States 3(2)(3) 6(2)(4) 7(2)(4) 6(2)(4) 5(2)(4) 4(2)(4) 5(2)(4) 1 States 3(2)(3) 5(2)(4) 6(2)(4) 5(2)(4) 5(2)(4) 4(2)(4) 5(2)(4) 1 Extended jump (indirect) Long jump (indirect) Long jump (direct address) Short jump (relative address) Jump indirect relative to the DPTR No operation (Jump never) LJMP SJMP JMP NOP Notes: 1. A shaded cell denotes an instruction in the C51 Architecture. 2. In internal execution only, add 1 to the number of states if the destination address is internal and odd. 3. Add 2 to the number of states if the destination address is external. 4. Add 3 to the number of states if the destination address is external. Table 34. Summary of Call and Return Instructions Absolute call Extended call Long call Return from subroutine Extended return from subroutine Return from interrupt Trap interrupt ACALL Mnemonic ACALL ECALL addr11 @DRk addr24 @WRj addr16 Binary Mode Comments Bytes Absolute subroutine call Extended subroutine call (indirect) Extended subroutine call Long subroutine call (indirect) Long subroutine call Return from subroutine Extended subroutine return Return from interrupt Jump to the trap interrupt vector 2 3 5 3 3 1 3 1 2 Source Mode Bytes 2 2 4 2 3 1 2 1 1 States 9(2)(3) 14(2)(3) 14(2)(3) 10(2)(3) 9(2)(3) 7(2) 9(2) 7(2)(4) 12(4) States 9(2)(3) 13(2)(3) 13(2)(3) 9(2)(3) 9(2)(3) 7(2) 8(2) 7(2)(4) 11(4) LCALL RET ERET RETI TRAP Notes: 1. A shaded cell denotes an instruction in the C51 Architecture. 2. In internal execution only, add 1 to the number of states if the destination/return address is internal and odd. 3. Add 2 to the number of states if the destination address is external. 4. Add 5 to the number of states if INTR= 1. 27 Rev. A - May 7, 1999 TSC80251G2D 8. Programming and Verifying Non-Volatile Memory 8.1 Internal Features The internal non-volatile memory of the TSC80251G2D derivatives contains five different areas: q q q q q Code Memory Configuration Bytes Lock Bits Encryption Array Signature Bytes 8.1.1 EPROM/OTPROM Devices All the internal non-volatile memory but the Signature Bytes of the TSC87251G2D products is made of EPROM cells. The Signature Bytes of the TSC87251G2D products are made of Mask ROM. The TSC87251G2D products are programmed and verified in the same manner as TEMIC's TSC87251G1A, using a SINGLE-PULSE algorithm, which programs at VPP= 12.75V using only one 100 s pulse per byte. This results in a programming time of less than 10 seconds for the 32 Kbytes on-chip code memory. The EPROM of the TSC87251G2D products in Window package is erasable by Ultra-Violet radiation(1) (UV). UV erasure set all the EPROM memory cells to one and allows a reprogramming. The quartz window must be covered with an opaque label(2) when the device is in operation. This is not so much to protect the EPROM array from inadvertent erasure, as to protect the RAM and other on-chip logic. Allowing light to impinge on the silicon die during device operation may cause a logical malfunction. The TSC87251G2D products in plastic packages are One Time Programmable (OTP). Then an EPROM cell cannot be reset by UV once programmed to zero. Notes: 1. The recommended erasure procedure is exposure to ultra-violet light (at 2537 A) to an integrated dose of at least 20 W-sec/cm2. Exposing the EPROM to an ultra-violet lamp of 12000 W/cm2 rating for 30 minutes should be sufficient. 2. Erasure of the EPROM begins to occur when the chip is exposed to light wavelength shorter than 4000 A. Since sunlight and fluorescent light have wavelength in this range, exposure to these light sources over an extended time (1 week in sunlight or 3 years in room-level fluorescent lighting) could cause inadvertent erasure. 8.1.2 Mask ROM Devices All the internal non-volatile memory of TSC83251G2D products is made of Mask ROM cells. They can only be verified by the user, using the same algorithm as the EPROM/OTPROM devices. 8.1.3 ROMless Devices The TSC80251G2D products do not include on-chip Configuration Bytes, Code Memory and Encryption Array. They only include Signature Bytes made of Mask ROM cells which can be read using the same algorithm as the EPROM/OTPROM devices. 8.2 Security Features In some microcontrollers applications, it is desirable that the user's program code be secured from unauthorized access. The TSC83251G2D and TSC87251G2D offer two kinds of protection for program code stored in the onchip array: q Program code in the on-chip Code Memory is encrypted when read out for verification if the Encryption Array is programmed. A three-level lock bit system restricts external access to the on-chip code memory. q Rev. A - May 7, 1999 28 TSC80251G2D 8.2.1 Lock Bit System The TSC87251G2D products implement 3 levels of security for User's program as described in Table 35. The TSC83251G2D products implement only the first level of security. Level 0 is the level of an erased part and does not enable any security features. Level 1 locks the programming of the User's internal Code Memory, the Configuration Bytes and the Encryption Array. Level 2 locks the verifying of the User's internal Code Memory. It is always possible to verify the Configuration Bytes and the Lock Bits. It is never possible to verify the Encryption Array. Level 3 locks the external execution. Table 35. Lock Bits Programming Level 0 1 2 3 Lock bits LB[2:0] 000 001 01x(3) 1xx(3) Internal Execution Enable Enable Enable Enable External Execution Enable Enable Enable Disable Verification Enable(1) Enable(1) Disable Disable Programming Enable Disable Disable Disable External PROM read (MOVC) Enable(2) Disable Disable Disable Notes: 1. Returns encrypted data if Encryption Array is programmed. 2. Returns non encrypted data. 3. x means don't care. Level 2 always enables level 1, and level 3 always enables levels 1 and 2. The security level may be verified according to Table 36. Table 36. Lock Bits Verifying Level 0 1 2 3 Note: 1. x means don't care. Lock bits Data(1) xxxxx000 xxxxx001 xxxxx01x xxxxx1xx 8.2.2 Encryption Array The TSC83251G2D and TSC87251G2D products include a 128-byte Encryption Array located in non-volatile memory outside the memory address space. During verification of the on-chip code memory, the seven low-order address bits also address the Encryption Array. As the byte of the code memory is read, it is exclusive-NOR'ed (XNOR) with the key byte from the Encryption Array. If the Encryption Array is not programmed (still all 1s), the user program code is placed on the data bus in its original, unencrypted form. If the Encryption Array is programmed with key bytes, the user program code is encrypted and cannot be used without knowledge of the key byte sequence. To preserve the secrecy of the encryption key byte sequence, the Encryption Array can not be verified. Cautions: 1. When a MOVC instruction is executed, the content of the ROM is not encrypted. In order to fully protect the user program code, the lock bit level 1 (see Table 35) must always be set when encryption is used. 2. If the encryption feature is implemented, the portion of the on-chip code memory that does not contain program code should be filled with "random" byte values to prevent the encryption key sequence from being revealed. 29 Rev. A - May 7, 1999 TSC80251G2D 8.3 Signature Bytes The TSC80251G2D derivatives contain factory-programmed Signature Bytes. These bytes are located in non-volatile memory outside the memory address space at 30h, 31h, 60h and 61h. To read the Signature Bytes, perform the procedure described in section 8.5, using the verify signature mode (see Table 39). Signature byte values are listed in Table 37. Table 37. Signature Bytes (Electronic ID) Signature Address Vendor Architecture Memory Revision TEMIC C251 32 Kbytes EPROM or OTPROM 32 Kbytes MaskROM or ROMless TSC80251G2D derivative 30h 31h 60h 61h Signature Data 58h 40h F7h 77h FDh 8.4 Programming Algorithm Figure 9 shows the hardware setup needed to program the TSC87251G2D EPROM/OTPROM areas: q q q The chip has to be put under reset and maintained in this state until the completion of the programming sequence. PSEN# and the other control signals (ALE and Port 0) have to be set to a high level. Then PSEN# has to be to forced to a low level after two clock cycles or more and it has to be maintained in this state until the completion of the programming sequence (see below). The voltage on the EA# pin must be set to VDD. The programming mode is selected according to the code applied on Port 0 (see Table 38). It has to be applied until the completion of this programming operation. The programming address is applied on Ports 1 and 3 which are respectively the Most Significant Byte (MSB) and the Least Significant Byte (LSB) of the address. The programming data are applied on Port 2. The EPROM Programming is done by raising the voltage on the EA# pin to VPP, then by generating a low level pulse on ALE/PROG# pin. The voltage on the EA# pin must be lowered to VDD before completing the programming operation. It is possible to alternate programming and verifying operation (See Paragraph 8.5). Please make sure the voltage on the EA# pin has actually been lowered to VDD before performing the verifying operation. PSEN# and the other control signals have to be released to complete a sequence of programming operations or a sequence of programming and verifying operations. q q q q q q q q Rev. A - May 7, 1999 30 TSC80251G2D VDD RST EA#/VPP ALE/PROG# PSEN# VDD VDD VPP 100 s pulses TSC87251G2D Mode P0[7:0] A[7:0] P3[7:0] XTAL1 4 to 12 MHz A[14:8] P1[7:0] Data P2[7:0] VSS/VSS1/VSS2 Figure 9. Setup for Programming Table 38. Programming Modes ROM Area(1) On-chip Code Memory Configuration Bytes RST 1 1 EA#/VPP VPP VPP PSEN# ALE/PROG#(2) 0 0 1 Pulse 1 Pulse P0 68h 69h P2 Data Data P1(MSB) P3(LSB) 16-bit Address 0000h-7FFFh (32 Kbytes) CONFIG0: FFF8h CONFIG1: FFF9h LB0: 0001h LB1: 0002h LB2: 0003h 0000h-007Fh Lock Bits Encryption Array 1 1 VPP VPP 0 0 1 Pulse 1 Pulse 6Bh 6Ch X Data Notes: 1. Signature Bytes are not user-programmable. 2. The ALE/PROG# pulse waveform is shown in Figure 31 page 54. 8.5 Verify Algorithm Figure 10 shows the hardware setup needed to verify the TSC87251G2D EPROM/OTPROM or TSC83251G2D ROM areas: q q q The chip has to be put under reset and maintained in this state until the completion of the verifying sequence. PSEN# and the other control signals (ALE and Port 0) have to be set to a high level. Then PSEN# has to be to forced to a low level after two clock cycles or more and it has to be maintained in this state until the completion of the verifying sequence (see below). The voltage on the EA# pin must be set to VDD and ALE must be set to a high level. The Verifying Mode is selected according to the code applied on Port 0. It has to be applied until the completion of this verifying operation. The verifying address is applied on Ports 1 and 3 which are respectively the MSB and the LSB of the address. Then device is driving the data on Port 2. It is possible to alternate programming and verification operation (see Paragraph 8.4). Please make sure the voltage on the EA# pin has actually been lowered to VDD before performing the verifying operation. PSEN# and the other control signals have to be released to complete a sequence of verifying operations or a sequence of programming and verifying operations. Rev. A - May 7, 1999 q q q q q q 31 TSC80251G2D Table 39. Verifying Modes ROM Area(1) On-chip code memory Configuration Bytes Lock Bits Signature Bytes RST 1 1 1 1 EA#/VPP 1 1 1 1 PSEN# 0 0 0 0 ALE/PROG# 1 1 1 1 P0 28h 29h 2Bh 29h P2 Data Data Data Data P1(MSB) P3(LSB) 16-bit Address 0000h-7FFFh (32 Kbytes) CONFIG0: FFF8h CONFIG1: FFF9h 0000h 0030h, 0031h, 0060h, 0061h Note: 1. To preserve the secrecy of on-chip code memory when encrypted, the Encryption Array can not be verified. VDD RST EA#/VPP ALE/PROG# PSEN# VDD VDD TSC8x251G2D Mode P0[7:0] P2[7:0] Data A[7:0] P3[7:0] XTAL1 4 to 12 MHz A[14:8] P1[7:0] VSS/VSS1/VSS2 Figure 10. Setup for Verifying Rev. A - May 7, 1999 32 TSC80251G2D 9. Absolute Maximum Rating and Operating Conditions 9.1 Absolute Maximum Rating Table 40. Absolute Maximum Ratings q q q q Storage Temperature ......................... -65 to +150C Voltage on any other Pin to VSS.... -0.5 to +6.5 V IOL per I/O Pin ................................. 15 mA Power Dissipation ............................. 1.5 W 9.2 Operating Conditions Table 41. Operating Conditions q Ambient Temperature Under Bias Commercial ....................................... 0 to +70C Industrial............................................ -40 to +85C VDD High Speed versions ......................... 4.5 to 5.5 V Low Voltage versions....................... 2.7 to 5.5 V q Note: Stressing the device beyond the "Absolute Maximum Ratings" may cause permanent damage. These are stress ratings only. Operation beyond the "operating conditions" is not recommended and extended exposure beyond the "Operating Conditions" may affect device reliability. Rev. A - May 7, 1999 33 TSC80251G2D 10. DC Characteristics - Commercial & Industrial 10.1 DC Characteristics: High Speed versions - Commercial & Industrial Table 42. DC Characteristics; VDD= 4.5 to 5.5 V, TA= -40 to +85C Symbol VIL VIL1(5) VIL2 VIH VIH1(5) VOL Parameter Input Low Voltage (except EA#, SCL, SDA) Input Low Voltage (SCL, SDA) Input Low Voltage (EA#) Input high Voltage (except XTAL1, RST, SCL, SDA) Input high Voltage (XTAL1, RST, SCL, SDA) Output Low Voltage (Ports 1, 2, 3) Output Low Voltage (Ports 0, ALE, PSEN#, Port 2 in Page Mode during External Address) Output high Voltage (Ports 1, 2, 3, ALE, PSEN#) Output high Voltage (Port 0, Port 2 in Page Mode during External Address) VDD data retention limit Logical 0 Input Current (Ports 1, 2, 3) Logical 1 Input Current (NMI) Input Leakage Current (Port 0) Logical 1-to-0 Transition Current (Ports 1, 2, 3 - AWAIT#) RST Pull-Down Resistor Pin Capacitance Operating Current Min -0.5 -0.5 0 0.2*VDD + 0.9 0.7*VDD Typical(4) Max 0.2*VDD - 0.1 0.3*VDD 0.2*VDD - 0.3 VDD + 0.5 VDD + 0.5 0.3 0.45 1.0 0.3 0.45 1.0 Units V V V V V V Test Conditions IOL= 100 A(1)(2) IOL= 1.6 mA(1)(2) IOL= 3.5 mA(1)(2) IOL= 200 A(1)(2) IOL= 3.2 mA(1)(2) IOL= 7.0 mA(1)(2) IOH= -10 A(3) IOH= -30 A(3) IOH= -60 A(3) IOH= -200 A IOH= -3.2 mA IOH= -7.0 mA VIN= 0.45 V VIN= VDD 0.45 V < VIN < VDD VIN= 2.0 V VOL1 V VOH VDD - 0.3 VDD - 0.7 VDD - 1.5 VDD - 0.3 VDD - 0.7 VDD - 1.5 1.8 - 50 + 50 10 - 650 40 110 10 20 25 35 5 6.5 9.5 2 12.5 25 30 40 6 8 12 20 13 75 225 V VOH1 V VRET IIL0 IIL1 ILI ITL RRST CIO IDD V A A A A k pF mA TA= 25C FOSC= 12 MHz FOSC= 16 MHz FOSC= 24 MHz FOSC= 12 MHz FOSC= 16 MHz FOSC= 24 MHz VRET < VDD < 5.5 V TA= 0 to +40C TA= 0 to +40C IDL Idle Mode Current mA IPD VPP IPP Power-Down Current Programming supply voltage Programming supply current A V mA 34 Rev. A - May 7, 1999 TSC80251G2D Notes: 1. Under steady-state (non-transient) conditions, IOL must be externally limited as follows: Maximum IOL per port pin: ............................................. 10 mA Maximum IOL per 8-bit port: Port 0................. 26 mA Ports 1-3............ 15 mA Maximum Total IOL for all: Output Pins ....... 71 mA If IOL exceeds the test conditions, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions. 2. Capacitive loading on Ports 0 and 2 may cause spurious noise pulses above 0.4 V on the low-level outputs of ALE and Ports 1, 2, and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins change from high to low. In applications where capacitive loading exceeds 100 pF, the noise pulses on these signals may exceed 0.8 V. It may be desirable to qualify ALE or other signals with a Schmitt Trigger or CMOS-level input logic. 3. Capacitive loading on Ports 0 and 2 causes the VOH on ALE and PSEN# to drop below the specification when the address lines are stabilizing. 4. Typical values are obtained using VDD= 5 V and TA= 25C. They are not tested and there is not guarantee on these values. 5. The input threshold voltage of SCL and SDA meets the I2C specification, so an input voltage below 0.3*VDD will be recognized as a logic 0 while an input voltage above 0.7*VDD will be recognized as a logic 1. 40 30 IDD/IDL (mA) 20 10 0 2 4 6 8 10 12 14 (1) 16 18 20 22 24 max Active mode (mA) typ Active mode (mA) max Idle mode (mA) typ Idle mode (mA) Note: 1. The clock prescaler is not used: FOSC= FXTAL. Frequency at XTAL (MHz) Figure 11. IDD/IDL Versus Frequency; VDD= 4.5 to 5.5 V Rev. A - May 7, 1999 35 TSC80251G2D 10.2 DC Characteristics: Low Voltage versions - Commercial & Industrial Table 43. DC Characteristics; VDD= 2.7 to 5.5 V, TA= -40 to +85C Symbol VIL VIL1(5) VIL2 VIH VIH1(5) VOL VOL1 Parameter Input Low Voltage (except EA#, SCL, SDA) Input Low Voltage (SCL, SDA) Input Low Voltage (EA#) Input high Voltage (except XTAL1, RST, SCL, SDA) Input high Voltage (XTAL1, RST, SCL, SDA) Output Low Voltage (Ports 1, 2, 3) Output Low Voltage (Ports 0, ALE, PSEN#, Port 2 in Page Mode during External Address) Output high Voltage (Ports 1, 2, 3, ALE, PSEN#) Output high Voltage (Port 0, Port 2 in Page Mode during External Address) VDD data retention limit Logical 0 Input Current (Ports 1, 2, 3 - AWAIT#) Logical 1 Input Current (NMI) Input Leakage Current (Port 0) Logical 1-to-0 Transition Current (Ports 1, 2, 3) RST Pull-Down Resistor Pin Capacitance Operating Current Min -0.5 -0.5 0 0.2*VDD + 0.9 0.7*VDD Typical(4) Max 0.2*VDD - 0.1 0.3*VDD 0.2*VDD - 0.3 VDD + 0.5 VDD + 0.5 0.45 0.45 Units V V V V V V V Test Conditions IOL= 0.8 mA(1)(2) IOL= 1.6 mA(1)(2) VOH VOH1 0.9*VDD 0.9*VDD V V IOH= -10 A(3) IOH= -40 A VRET IIL0 IIL1 ILI ITL RRST CIO IDD 1.8 - 50 + 50 10 - 650 40 110 10 4 8 9 11 0.5 1.5 2 3 1 8 11 12 14 1 4 5 7 10 225 V A A A A k pF mA TA= 25C 5 MHz, VDD < 3.6 V 10 MHz, VDD < 3.6 V 12 MHz, VDD < 3.6 V 16 MHz, VDD < 3.6 V 5 MHz, VDD < 3.6 V 10 MHz, VDD < 3.6 V 12 MHz, VDD < 3.6 V 16 MHz, VDD < 3.6 V VRET < VDD < 3.6 V VIN= 0.45 V VIN= VDD 0.45 V < VIN < VDD VIN= 2.0 V IDL Idle Mode Current mA IPD Power-Down Current A 36 Rev. A - May 7, 1999 TSC80251G2D Notes: 1. Under steady-state (non-transient) conditions, IOL must be externally limited as follows: Maximum IOL per port pin: ............................................. 10 mA Maximum IOL per 8-bit port: Port 0................. 26 mA Ports 1-3............ 15 mA Maximum Total IOL for all: Output Pins ....... 71 mA If IOL exceeds the test conditions, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions. 2. Capacitive loading on Ports 0 and 2 may cause spurious noise pulses above 0.4 V on the low-level outputs of ALE and Ports 1, 2, and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins change from high to low. In applications where capacitive loading exceeds 100 pF, the noise pulses on these signals may exceed 0.8 V. It may be desirable to qualify ALE or other signals with a Schmitt Trigger or CMOS-level input logic. 3. Capacitive loading on Ports 0 and 2 causes the VOH on ALE and PSEN# to drop below the specification when the address lines are stabilizing. 4. Typical values are obtained using VDD= 3 V and TA= 25C. They are not tested and there is not guarantee on these values. 5. The input threshold voltage of SCL and SDA meets the I2C specification, so an input voltage below 0.3*VDD will be recognized as a logic 0 while an input voltage above 0.7*VDD will be recognized as a logic 1. 15 IDD/IDL (mA) 10 5 0 2 4 6 8 10 12 14 16 max Active mode (mA) typ Active mode (mA) max Idle mode (mA) typ Idle mode (mA) Note: 1. The clock prescaler is not used: FOSC= FXTAL. Frequency at XTAL(1) (MHz) Figure 12. IDD/IDL Versus XTAL Frequency; VDD= 2.7 to 3.6 V Rev. A - May 7, 1999 37 TSC80251G2D 10.3 DC Characteristics: IDD, IDL and IPD Test Conditions VDD RST VDD VDD IDD TSC80251G2D P0 (NC) Clock Signal XTAL2 XTAL1 VSS All other pins are unconnected EA# VDD Figure 13. IDD Test Condition, Active Mode VDD RST VDD IDL TSC80251G2D P0 (NC) Clock Signal XTAL2 XTAL1 VSS All other pins are unconnected EA# VDD Figure 14. IDL Test Condition, Idle Mode VDD RST VDD IPD TSC80251G2D P0 (NC) XTAL2 XTAL1 VSS All other pins are unconnected EA# VDD Figure 15. IPD Test Condition, Power-Down Mode 38 Rev. A - May 7, 1999 TSC80251G2D 11. AC Characteristics - Commercial & Industrial 11.1 AC Characteristics - External Bus Cycles Definition of symbols Table 44. External Bus Cycles Timing Symbol Definitions Signals A D L Q R W Address Data In ALE Data Out RD#/PSEN# WR# H L V X Z Conditions High Low Valid No Longer Valid Floating Timings Test conditions: capacitive load on all pins= 50 pF. Table 45 and Table 46 list the AC timing parameters for the TSC80251G2D derivatives with no wait states. External wait states can be added by extending PSEN#/RD#/WR# and or by extending ALE. In these tables, Note 2 marks parameters affected by one ALE wait state, and Note 3 marks parameters affected by PSEN#/RD#/WR# wait states. Figure 16 to Figure 21 show the bus cycles with the timing parameters. Rev. A - May 7, 1999 39 TSC80251G2D Table 45. Bus Cycles AC Timings; VDD= 4.5 to 5.5 V, TA= -40 to 85C 12 MHz Symbol TOSC TLHLL TAVLL TLLAX TRLRH TLLRL (1) 16 MHz Min 62 58 58 11 121 124 14 70 24 MHz Unit Min 41 38 37 3 78 81 6 40 Parameter Min 1/FOSC ALE Pulse Width Address Valid to ALE Low Address hold after ALE Low RD#/PSEN# Pulse Width WR# Pulse Width ALE Low to RD#/PSEN# Low ALE High to Address Hold RD#/PSEN# Low to Valid Data Data Hold After RD#/PSEN# High Address Hold After RD#/PSEN# High RD#/PSEN# Low to Address Float Instruction Float After RD#/PSEN# High Data Float After RD#/PSEN# High RD#/PSEN# high to ALE High (Instruction) RD#/PSEN# high to ALE High (Data) WR# High to ALE High Address (P0) Valid to Valid Data In Address (P2) Valid to Valid Data In Address (P0) Valid to Valid Instruction In Data Hold after Address Hold Address Valid to RD# Low Address (P0) Valid to WR# Low Address (P2) Valid to WR# Low Data Hold after WR# High Data Valid to WR# High WR# High to Address Hold 0 100 100 158 90 133 167 49 215 215 250 306 150 0 70 70 115 69 102 125 0 0 0 45 215 43 169 169 175 223 109 0 40 40 74 32 72 84 83 78 78 19 162 165 22 99 146 0 0 0 40 165 31 115 115 105 140 68 Max Max Max ns ns(2) ns(2) ns ns(3) ns(3) ns ns(2) 61 ns(3) ns ns 0 30 115 ns ns ns ns ns ns ns(2)(3) ns(2)(3) ns(3) ns ns(2) ns(2) ns(2) ns ns(3) ns TWLWH (1) TLHAX TRLDV(1) TRHDX(1) TRHAX (1) 104 0 0 TRLAZ(1) TRHDZ1 TRHDZ2 TRHLH1 TRHLH2 TWHLH TAVDV1 TAVDV2 TAVDV3 TAXDX TAVRL(1) TAVWL1 TAVWL2 TWHQX TQVWH TWHAX Notes: 1. Specification for PSEN# are identical to those for RD#. 2. If a wait state is added by extending ALE, add 2*TOSC. 3. If wait states are added by extending RD#/PSEN#/WR#, add 2N*TOSC (N= 1..3). 40 Rev. A - May 7, 1999 TSC80251G2D Table 46. Bus Cycles AC Timings; VDD= 2.7 to 5.5 V, TA= -40 to 85C 12 MHz Symbol TOSC TLHLL TAVLL TLLAX TRLRH TLLRL (1) 16 MHz Unit Min 62 52 51 6 121 124 11 57 Parameter Min 1/FOSC ALE Pulse Width Address Valid to ALE Low Address hold after ALE Low RD#/PSEN# Pulse Width WR# Pulse Width ALE Low to RD#/PSEN# Low ALE High to Address Hold RD#/PSEN# Low to Valid Data Data Hold After RD#/PSEN# High Address Hold After RD#/PSEN# High RD#/PSEN# Low to Address Float Instruction Float After RD#/PSEN# High Data Float After RD#/PSEN# High RD#/PSEN# high to ALE High (Instruction) RD#/PSEN# high to ALE High (Data) WR# High to ALE High Address (P0) Valid to Valid Data In Address (P2) Valid to Valid Data In Address (P0) Valid to Valid Instruction In Data Hold after Address Hold Address Valid to RD# Low Address (P0) Valid to WR# Low Address (P2) Valid to WR# Low Data Hold after WR# High Data Valid to WR# High WR# High to Address Hold 0 111 111 158 82 135 168 60 226 226 289 296 144 0 64 64 116 66 103 125 0 0 0 59 225 47 172 172 160 211 98 83 72 71 14 163 165 17 90 133 0 0 0 48 175 Max Max ns ns(2) ns(2) ns ns(3) ns(3) ns ns(2) 92 ns(3) ns ns ns ns ns ns ns ns ns(2)(3) ns(2)(3) ns(3) ns ns(2) ns(2) ns(2) ns ns(3) ns TWLWH (1) TLHAX TRLDV(1) TRHDX(1) TRHAX(1) TRLAZ(1) TRHDZ1 TRHDZ2 TRHLH1 TRHLH2 TWHLH TAVDV1 TAVDV2 TAVDV3 TAXDX TAVRL(1) TAVWL1 TAVWL2 TWHQX TQVWH TWHAX Notes: 1. Specification for PSEN# are identical to those for RD#. 2. If a wait state is added by extending ALE, add 2*TOSC. 3. If wait states are added by extending RD#/PSEN#/WR#, add 2N*TOSC (N= 1..3). Rev. A - May 7, 1999 41 TSC80251G2D Waveforms in Non-Page Mode ALE TLHLL(1) TLLRL(1) TRLRH(1) TRHLH1 PSEN# TRLDV(1) TRLAZ TLHAX(1) TAVLL P0 (1) TRHDZ1 TRHDX D7:0 Instruction In TRHAX TLLAX A7:0 TAVRL (1) TAVDV1(1) TAVDV2(1) P2/A16/A17 A15:8/A16/A17 Note: 1. The value of this parameter depends on wait states. See Table 45 and Table 46. Figure 16. External Bus Cycle: Code Fetch (Non-Page Mode) ALE TLHLL(1) TLLRL(1) TRLRH(1) TRHLH2 RD#/PSEN# TRLDV(1) TRLAZ TLHAX(1) TAVLL(1) P0 TLLAX A7:0 TAVRL (1) TRHDZ2 TRHDX D7:0 Data In TRHAX TAVDV1(1) TAVDV2(1) P2/A16/A17 A15:8/A16/A17 Note: 1. The value of this parameter depends on wait states. See Table 45 and Table 46. Figure 17. External Bus Cycle: Data Read (Non-Page Mode) 42 Rev. A - May 7, 1999 TSC80251G2D ALE TLHLL(1) TWLWH(1) TWHLH WR# TLHAX(1) TAVLL(1) P0 TLLAX A7:0 TAVWL1(1) TAVWL2(1) P2/A16/A17 A15:8/A16/A17 TQVWH TWHQX D7:0 Data Out TWHAX Note: 1. The value of this parameter depends on wait states. See Table 45 and Table 46. Figure 18. External Bus Cycle: Data Write (Non-Page Mode) Waveforms in Page Mode ALE TLHLL(1) TLLRL(1) PSEN#(3) TRLDV(1) TRLAZ TLHAX(1) TAVLL(1) P2 TLLAX A15:8 TAVRL (1) TRHDZ1 TRHDX D7:0 Instruction In TAXDX TAVDV3(1) A7:0/A16/A17 Page Hit(2) TRHAX D7:0 Instruction In TAVDV1(1) TAVDV2(1) P0/A16/A17 A7:0/A16/A17 Page Miss(2) Notes: 1. The value of this parameter depends on wait states. See Table 45 and Table 46. 2. A page hit (i.e., a code fetch to the same 256-byte "page" as the previous code fetch) requires one state (2*TOSC); a page miss requires two states (4*TOSC). 3. During a sequence of page hits, PSEN# remains low until the end of the last page-hit cycle. Figure 19. External Bus Cycle: Code Fetch (Page Mode) Rev. A - May 7, 1999 43 TSC80251G2D ALE TLHLL(1) TLLRL(1) TRLRH(1) TRHLH2 RD#/PSEN# TRLDV(1) TRLAZ TLHAX(1) TAVLL(1) P2 TLLAX A15:8 TAVRL(1) TAVDV1(1) TAVDV2(1) P0/A16/A17 A7:0/A16/A17 TRHDZ2 TRHDX D7:0 Data In TRHAX Note: 1. The value of this parameter depends on wait states. See Table 45 and Table 46. Figure 20. External Bus Cycle: Data Read (Page Mode) ALE TLHLL(1) TWLWH(1) TWHLH WR# TLHAX(1) TAVLL(1) P2 TLLAX A15:8 TAVWL1 TAVWL2(1) P0/A16/A17 A7:0/A16/A17 (1) TQVWH TWHQX D7:0 Data Out TWHAX Note: 1. The value of this parameter depends on wait states. See Table 45 and Table 46. Figure 21. External Bus Cycle: Data Write (Page Mode) 44 Rev. A - May 7, 1999 TSC80251G2D 11.2 AC Characteristics - Real-Time Synchronous Wait State Definition of symbols Table 47. Real-Time Synchronous Wait Timing Symbol Definitions Signals C R W Y WCLK RD#/PSEN# WR# WAIT# L V X Conditions Low Valid No Longer Valid Timings Table 48. Real-Time Synchronous Wait AC Timings; VDD= 2.7 to 5.5 V, TA= -40 to 85C Symbol TCLYV TCLYX TRLYV TRLYX TWLYV TWLYX Parameter Wait Clock Low to Wait Set-up Wait Hold after Wait Clock Low PSEN#/RD# Low to Wait Set-up Wait Hold after PSEN#/RD# Low WR# Low to Wait Set-up Wait Hold after WR# Low Min 0 2W*TOSC + 5 0 2W*TOSC + 5 0 2W*TOSC + 5 Max TOSC - 20 (1+2W)*TOSC - 20 TOSC - 20 (1+2W)*TOSC - 20 TOSC - 20 (1+2W)*TOSC - 20 Unit ns ns ns ns ns ns Waveforms State 1 WCLK TCLYXmin ALE TCLYV RD#/PSEN# TRLYXmax TRLYXmin TRLYV WAIT# P0 P2 A7:0 A15:8 D7:0 stretched stretched A7:0 A15:8 RD#/PSEN# stretched TCLYXmax State 2 State 3 State 1 (next cycle) Figure 22. Real-time Synchronous Wait State: Code Fetch/Data Read Rev. A - May 7, 1999 45 TSC80251G2D State 1 WCLK TCLYXmin ALE TCLYV RD#/PSEN# TWLYXmax TWLYXmin TWLYV WAIT# P0 P2 A7:0 A15:8 D7:0 stretched stretched WR# stretched TCLYXmax State 2 State 3 State 1 (next cycle) Figure 23. Real-time Synchronous Wait State: Data Write 11.3 AC Characteristics - Real-Time Asynchronous Wait State Definition of symbols Table 49. Real-Time Asynchronous Wait Timing Symbol Definitions Signals S Y PSEN#/RD#/WR# AWAIT# L V X Conditions Low Valid No Longer Valid Timings Table 50. Real-Time Asynchronous Wait AC Timings; VDD= 2.7 to 5.5 V, TA= -40 to 85C Symbol TSLYV TSLYX Parameter PSEN#/RD#/WR# Low to Wait Set-up Wait Hold after PSEN#/RD#/WR# Low Min (2N-1)*TOSC + 10 Max TOSC - 10 Unit ns ns(1) Note: 1. N is the number of wait states added (N 1). Waveforms RD#/PSEN#/WR# TSLYX TSLYV AWAIT# Figure 24. Real-time Asynchronous Wait State Timings 46 Rev. A - May 7, 1999 TSC80251G2D 11.4 AC Characteristics - Serial Port in Shift Register Mode Definition of symbols Table 51. Serial Port Timing Symbol Definitions Signals D Q X Data In Data Out Clock H L V X Conditions High Low Valid No Longer Valid Timings Table 52. Serial Port AC Timing -Shift Register Mode; VDD= 2.7 to 5.5 V, TA= -40 to 85C 12 MHz Symbol TXLXL TQVXH TXHQX TXHDX TXHDV 16 MHz Min 749 625 124 0 24 MHz(1) Unit Min 500 417 82 0 Parameter Min Serial Port Clock Cycle Time Output Data Setup to Clock Rising Edge Output Data hold after Clock Rising Edge Input Data Hold after Clock Rising Edge Clock Rising Edge to Input Data Valid 998 833 165 0 974 Max Max Max ns ns ns ns 482 ns 732 Note: 1. For high speed versions only. Waveforms TXLXL TXD TQVXH TXHQX RXD (Out) 0 TXHDV RXD (In) Valid Valid 1 2 TXHDX Valid Valid Valid Valid Valid 3 4 5 6 Set TI(1) 7 Set RI(1) Valid Note: 1. TI and RI are set during S1P1 of the peripheral cycle following the shift of the eight bit. Figure 25. Serial Port Waveforms - Shift Register Mode Rev. A - May 7, 1999 47 TSC80251G2D 11.5 AC Characteristics - SSLC: I2C Interface Timings Table 53. I2C Interface AC Timing; VDD= 2.7 to 5.5 V, TA= -40 to 85C Symbol THD; STA TLOW THIGH TRC TFC TSU; DAT1 TSU; DAT2 TSU; DAT3 THD; DAT TSU; STA TSU; STO TBUF TRD TFD Parameter Start condition hold time SCL low time SCL high time SCL rise time SCL fall time Data set-up time SDA set-up time (before repeated START condition) SDA set-up time (before STOP condition) Data hold time Repeated START set-up time STOP condition set-up time Bus free time SDA rise time SDA fall time INPUT Min 14*TCLCL (4) OUTPUT Max Min 4.0 s(1) 4.7 s(1) 4.0 s(1) 1 s 0.3 s 20*TCLCL(4)- TRD 1 s(1) 8*TCLCL(4) 8*TCLCL(4) - TFC 4.7 s(1) 4.0 s(1) 4.7 s(1) 1 s 0.3 s -(2) 0.3 s(3) -(2) 0.3 s(3) Max 16*TCLCL(4) 14*TCLCL (4) 250 ns 250 ns 250 ns 0 ns 14*TCLCL(4) 14*TCLCL(4) 14*TCLCL(4) Notes: 1. At 100 kbit/s. At other bit-rates this value is inversely proportional to the bit-rate of 100 kbit/s. 2. Determined by the external bus-line capacitance and the external bus-line pull-up resistor, this must be < 1 s. 3. Spikes on the SDA and SCL lines with a duration of less than 3*TCLCL will be filtered out. Maximum capacitance on bus-lines SDA and SCL= 400 pF. 4. TCLCL= TOSC= one oscillator clock period. Waveforms START or Repeated START condition TRD Repeated START condition START condition STOP condition TSU;STA 0.7 VDD 0.3 VDD SDA (INPUT/OUTPUT) TFD TRC TFC TSU;STO TSU;DAT3 0.7 VDD 0.3 VDD THD;STA TLOW THIGH TSU;DAT1 THD;DAT TSU;DAT2 TBUF SCL (INPUT/OUTPUT) Figure 26. I2C Waveforms 48 Rev. A - May 7, 1999 TSC80251G2D 11.6 AC Characteristics - SSLC: SPI Interface Definition of symbols Table 54. SPI Interface Timing Symbol Definitions Signals C I O S Clock Data In Data Out SS# H L V X Z Conditions High Low Valid No Longer Valid Floating Timings Table 55. SPI Interface AC Timing; VDD= 2.7 to 5.5 V, TA= -40 to 85C Symbol Slave mode TCHCH TCHCX TCLCX TSLCH, TSLCL TIVCL, TIVCH TCLIX, TCHIX TCLOV, TCHOV TCLOX, TCHOX TCLSH, TCHSH TIVCL, TIVCH TCLIX, TCHIX TSLOV TSHOX TSHSL TILIH TIHIL TOLOH TOHOL (1) Parameter Min Max Unit Clock Period Clock High Time Clock Low Time SS# Low to Clock edge Input Data Valid to Clock Edge Input Data Hold after Clock Edge Output Data Valid after Clock Edge Output Data Hold Time after Clock Edge SS# High after Clock Edge Input Data Valid to Clock Edge Input Data Hold after Clock Edge SS# Low to Output Data Valid Output Data Hold after SS# High SS# High to SS# Low Input Rise Time Input Fall Time Output Rise time Output Fall Time 8 3.2 3.2 200 100 100 100 0 0 100 100 130 130 (2) 2 2 100 100 TOSC TOSC TOSC ns ns ns ns ns ns ns ns ns ns s s ns ns Rev. A - May 7, 1999 49 TSC80251G2D Symbol Master mode TCHCH TCHCX TCLCX TIVCL, TIVCH TCLIX, TCHIX TCLOV, TCHOV TCLOX, TCHOX TILIH TIHIL TOLOH (3) Parameter Min Max Unit Clock Period Clock High Time Clock Low Time Input Data Valid to Clock Edge Input Data Hold after Clock Edge Output Data Valid after Clock Edge Output Data Hold Time after Clock Edge Input Data Rise Time Input Data Fall Time Output Data Rise time 4 1.6 1.6 50 50 65 0 2 2 50 50 TOSC TOSC TOSC ns ns ns ns s s ns ns TOHOL Output Data Fall Time Notes: 1. Capacitive load on all pins= 200 pF in slave mode. 2. The value of this parameter depends on software. 3. Capacitive load on all pins= 100 pF in master mode. Waveforms SS#(1) (output) TCHCH SCK (SSCPOL= 0) (output) SCK (SSCPOL= 1) (output) TIVCH TCHIX TIVCL TCLIX MISO (input) MSB IN BIT 6 TCLOV TCHOV MOSI (output) Note: 1. SS# handled by software. Port Data MSB OUT BIT 6 LSB OUT LSB IN TCLOX TCHOX Port Data TCLCH TCHCX TCLCX TCHCL Figure 27. SPI Master Waveforms (SSCPHA= 0) 50 Rev. A - May 7, 1999 TSC80251G2D SS#(1) (output) TCHCH SCK (SSCPOL= 0) (output) SCK (SSCPOL= 1) (output) TIVCH TCHIX TIVCL TCLIX MISO (input) MSB IN TCLOV TCHOV MOSI (output) Note: 1. SS# handled by software. Port Data MSB OUT BIT 6 TCLOX TCHOX BIT 6 LSB OUT Port Data LSB IN TCLCH TCHCX TCLCX TCHCL Figure 28. SPI Master Waveforms (SSCPHA= 1) SS# (input) TSLCH TSLCL SCK (SSCPOL= 0) (input) SCK (SSCPOL= 1) (input) TSLOV MISO (output) SLAVE MSB OUT TIVCH TCHIX TIVCL TCLIX MOSI (input) MSB IN BIT 6 LSB IN TCHCH TCLCH TCLSH TCHSH TSHSL TCHCX TCLCX TCHCL TCLOV TCHOV BIT 6 TCLOX TCHOX SLAVE LSB OUT (1) TSHOX Note: 1. Not Defined but normally MSB of character just received. Figure 29. SPI Slave Waveforms (SSCPHA= 0) Rev. A - May 7, 1999 51 TSC80251G2D SS# (input) TSLCH TSLCL SCK (SSCPOL= 0) (input) SCK (SSCPOL= 1) (input) TSLOV MISO (output) (1) TCHCH TCLCH TCLSH TCHSH TSHSL TCHCX TCLCX TCHCL TCHOV TCLOV BIT 6 TCHOX TCLOX SLAVE LSB OUT TSHOX SLAVE MSB OUT TIVCH TCHIX TIVCL TCLIX MOSI (input) MSB IN BIT 6 LSB IN Note: 1. Not Defined but generally the LSB of the character which has just been received. Figure 30. SPI Slave Waveforms (SSCPHA= 1) 52 Rev. A - May 7, 1999 TSC80251G2D 11.7 AC Characteristics - EPROM Programming and Verifying Definition of symbols Table 56. EPROM Programming and Verifying Timing Symbol Definitions Signals A E G Q S Address Enable: mode set on Port 0 Program Data Out Supply (VPP) H L V X Z Conditions High Low Valid No Longer Valid Floating Timings Table 57. EPROM Programming AC timings; VDD= 4.5 to 5.5 V, TA= 0 to 40C Symbol TOSC TAVGL TGHAX TDVGL TGHDX TELSH TSHGL TGHSL TSLEH TGLGH XTAL1 Period Address Setup to PROG# low Address Hold after PROG# low Data Setup to PROG# low Data Hold after PROG# ENABLE High to VPP VPP Setup to PROG# low VPP Hold after PROG# ENABLE Hold after VPP PROG# Width Parameter Min 83.5 48 48 48 48 48 10 10 0 90 Max 250 Unit ns TOSC TOSC TOSC TOSC TOSC s s ns s 110 Table 58. EPROM Verifying AC timings; VDD= 4.5 to 5.5 V, VDD= 2.7 to 5.5 V, TA= 0 to 40C Symbol TOSC TAVQV TAXQX TELQV TEHQZ XTAL1 Period Address to Data Valid Address to Data Invalid ENABLE low to Data Valid Data Float after ENABLE 0 0 0 48 48 Parameter Min 83.5 Max 250 48 Unit ns TOSC ns TOSC TOSC Rev. A - May 7, 1999 53 TSC80251G2D Waveforms P1= A15:8 P3= A7:0 TAVGL P2= D7:0 TDVGL VPP EA#/VPP VDD VSS ALE/PROG# TELSH P0 Mode= 68h, 69h, 6Bh or 6Ch TSLEH TSHGL TGLGH TGHSL Data TGHDX Address TGHAX Figure 31. EPROM Programming Waveforms P1= A15:8 P3= A7:0 TAVQV P2= D7:0 TELQV P0 Address TAXQX Data TEHQZ Mode= 28h, 29h or 2Bh Figure 32. EPROM Verifying Waveforms 54 Rev. A - May 7, 1999 TSC80251G2D 11.8 AC Characteristics - External Clock Drive and Logic Level References Definition of symbols Table 59. External Clock Timing Symbol Definitions Signals C Clock H L X Conditions High Low No Longer Valid Timings Table 60. External Clock AC Timings; VDD= 4.5 to 5.5 V, TA= -40 to +85C Symbol FOSC TCHCX TCLCX TCLCH TCHCL Oscillator Frequency High Time Low Time Rise Time Fall Time 10 10 3 3 Parameter Min Max 24 Unit MHz ns ns ns ns Waveforms TCLCH VDD - 0.5 0.45 V VIH1 TCLCX TCHCL TCLCL TCHCX VIL Figure 33. External Clock Waveform INPUTS VDD - 0.5 0.45 V 0.2 VDD + 0.9 0.2 VDD - 0.1 OUTPUTS VIH min VIL max Note: During AC testing, all inputs are driven at VDD -0.5 V for a logic 1 and 0.45 V for a logic 0. Timing measurements are made on all outputs at VIH min for a logic 1 and VIL max for a logic 0. Figure 34. AC Testing Input/Output Waveforms VLOAD VLOAD + 0.1 V VLOAD - 0.1 V Timing Reference Points VOH - 0.1 V VOL + 0.1 V Note: For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs and begins to float when a 100 mV change from the loading VOH/VOL level occurs with IOL/IOH= 20 mA. Figure 35. Float Waveforms Rev. A - May 7, 1999 55 TSC80251G2D 12. Packages 12.1 List of Packages q q q q q PDIL 40 CDIL 40 with window PLCC 44 CQPJ 44 with window VQFP 44 (10x10) 12.2 PDIL 40 - Mechanical Outline Figure 36. Plastic Dual In Line Table 61. PDIL Package Size MM Min A A1 A2 B B1 C D E E1 e eA eB L D1 2.93 0.13 0.38 3.18 0.36 0.76 0.20 50.29 15.24 12.32 2.54 B.S.C. 15.24 B.S.C. 17.78 3.81 .115 .005 INCH Max 5.08 4.95 0.56 1.78 0.38 53.21 15.87 14.73 Min .015 .125 .014 .030 .008 1.980 .600 .485 .100 B.S.C. .600 B.S.C. Max .200 .195 .022 .070 .015 2.095 .625 .580 .700 .150 - Rev. A - May 7, 1999 56 TSC80251G2D 12.3 CDIL 40 with Window - Mechanical Outline Figure 37. Ceramic Dual In Line Table 62. CDIL Package Size MM Min A b b2 c D E e eA L Q S1 a N 3.18 0.38 0.13 0 - 15 40 0.36 1.14 0.20 13.06 2.54 B.S.C. 15.24 B.S.C. 5.08 1.40 .125 .015 .005 0 - 15 INCH Max 5.71 0.58 1.65 0.38 53.47 15.37 Min .014 .045 .008 .514 .100 B.S.C. .600 B.S.C. Max .225 .023 .065 .015 2.105 .605 .200 .055 - 57 Rev. A - May 7, 1999 TSC80251G2D 12.4 PLCC 44 - Mechanical Outline Figure 38. Plastic Lead Chip Carrier Table 63. PLCC Package Size MM Min A A1 D D1 D2 E E1 E2 e G H J K Nd Ne 1.07 1.07 0.51 0.33 11 11 4.20 2.29 17.40 16.44 14.99 17.40 16.44 14.99 1.27 BSC 1.22 1.42 0.53 .042 .042 .020 .013 11 11 INCH Max 4.57 3.04 17.65 16.66 16.00 17.65 16.66 16.00 Min .165 .090 .685 .647 .590 .685 .647 .590 .050 BSC Max .180 .120 .695 .656 .630 .695 .656 .630 .048 .056 .021 Rev. A - May 7, 1999 58 TSC80251G2D 12.5 CQPJ 44 with Window - Mechanical Outline Figure 39. Ceramic Quad Pack J Table 64. CQPJ Package size MM Min A C D-E D1 - E1 e f J Q R N1 N2 0.43 0.86 15.49 0.86 TYP 11 11 0.15 17.40 16.36 1.27 TYP 0.53 1.12 16.00 .017 .034 .610 .034 TYP 11 11 INCH Max 4.90 0.25 17.55 16.66 Min .006 .685 .644 .050 TYP Max .193 .010 .691 .656 .021 .044 .630 59 Rev. A - May 7, 1999 TSC80251G2D 12.6 VQFP 44 (10x10) - Mechanical Outline Figure 40. Shrink Quad Flat Pack (Plastic) Table 65. VQFP Package Size MM Min A A1 A2 A3 D D1 E E1 J L e f 1.35 11.90 9.90 11.90 9.90 0.05 0.45 0.80 BSC 0.35 BSC 0.64 REF 0.64 REF 1.45 12.10 10.10 12.10 10.10 0.75 .053 .468 .390 .468 .390 .002 .018 .0315 BSC .014 BSC INCH Max 1.60 Min .025 REF .025REF Max .063 .057 .476 .398 .476 .398 6 .030 Rev. A - May 7, 1999 60 TSC80251G2D 13. Ordering Information 13.1 TSC80251G2D ROMless TEMIC Part Number ROM Description High Speed Versions 4.5 to 5.5 V, Commercial and Industrial TSC80251G2D-16CB TSC80251G2D-24CB TSC80251G2D-24CED TSC80251G2D-24IA TSC80251G2D-24IB ROMless ROMless ROMless ROMless ROMless 16 MHz, Commercial 0 to 70C, PLCC 44 24 MHz, Commercial 0 to 70C, PLCC 44 24 MHz, Commercial 0 to 70C, VQFP 44, Dry pack(1) 24 MHz, Industrial -40 to 85C, PDIL 40 24 MHz, Industrial -40 to 85C, PLCC 44 Low Voltage Versions 2.7 to 5.5 V, Commercial TSC80251G2D-L16CB TSC80251G2D-L16CED Note: 1. Dry Pack mandatory for VQFP package. ROMless ROMless 16 MHz, Commercial, PLCC 44 16 MHz, Commercial, VQFP 44, Dry pack(1) 13.2 TSC83251G1D 16 Kbytes Mask ROM TEMIC Part Number(2) ROM Description High Speed Versions 4.5 to 5.5 V, Commercial and Industrial TSC251G1Dxxx-16CB TSC251G1Dxxx-24CB TSC251G1Dxxx-24CED TSC251G1Dxxx-24IA TSC251G1Dxxx-24IB 16K MaskROM 16K MaskROM 16K MaskROM 16K MaskROM 16K MaskROM 16 MHz, Commercial 0 to 70C, PLCC 44 24 MHz, Commercial 0 to 70C, PLCC 44 24 MHz, Commercial 0 to 70C, VQFP 44, Dry pack(1) 24 MHz, Industrial -40 to 85C, PDIL 40 24 MHz, Industrial -40 to 85C, PLCC 44 Low Voltage Versions 2.7 to 5.5 V, Commercial TSC251G1Dxxx-L16CB TSC251G1Dxxx-L16CED 16K MaskROM 16K MaskROM 16 MHz, Commercial 0 to 70C, PLCC 44 16 MHz, Commercial 0 to 70C, VQFP 44, Dry pack(1) Notes: 1. Dry Pack mandatory for VQFP package. 2. xxx: means ROM code, is Cxxx in case of encrypted code. 13.3 TSC83251G2D 32 Kbytes MaskROM TEMIC Part Number(2) ROM Description High Speed Versions 4.5 to 5.5 V, Commercial and Industrial TSC251G2Dxxx-16CB TSC251G2Dxxx-24CB TSC251G2Dxxx-24CED TSC251G2Dxxx-24IA TSC251G2Dxxx-24IB 32K MaskROM 32K MaskROM 32K MaskROM 32K MaskROM 32K MaskROM 16 MHz, Commercial 0 to 70C, PLCC 44 24 MHz, Commercial 0 to 70C, PLCC 44 24 MHz, Commercial 0 to 70C, VQFP 44, Dry pack(1) 24 MHz, Industrial -40 to 85C, PDIL 40 24 MHz, Industrial -40 to 85C, PLCC 44 Low Voltage Versions 2.7 to 5.5 V, Commercial TSC251G2Dxxx-L16CB TSC251G2Dxxx-L16CED 32K MaskROM 32K MaskROM 16 MHz, Commercial 0 to 70C, PLCC 44 16 MHz, Commercial 0 to 70C, VQFP 44, Dry pack(1) Notes: 1. Dry Pack mandatory for VQFP package. 2. xxx: means ROM code, is Cxxx in case of encrypted code. Rev. A - May 7, 1999 61 TSC80251G2D 13.4 TSC87251G2D OTPROM TEMIC Part Number ROM Description High Speed Versions 4.5 to 5.5 V, Commercial and Industrial TSC87251G2D-16CB TSC87251G2D-24CB TSC87251G2D-24CED TSC87251G2D-24IA TSC87251G2D-24IB 32K OTPROM 32K OTPROM 32K OTPROM 32K OTPROM 32K OTPROM 16 MHz, Commercial 0 to 70C, PLCC 44 24 MHz, Commercial 0 to 70C, PLCC 44 24 MHz, Commercial 0 to 70C, VQFP 44, Dry pack(1) 24 MHz, Industrial -40 to 85C, PDIL 40 24 MHz, Industrial -40 to 85C, PLCC 44 Low Voltage Versions 2.7 to 5.5 V, Commercial TSC87251G2D-L16CB TSC87251G2D-L16CED Note: 1. Dry Pack mandatory for VQFP package. 32K OTPROM 32K OTPROM 16 MHz, Commercial 0 to 70C, PLCC 44 16 MHz, Commercial 0 to 70C, VQFP 44, Dry pack(1) 13.5 TSC87251G2D EPROM - UV Window package TEMIC Part Number High Speed Versions 4.5 to 5.5 V, Industrial TSC87251G2D-24IC TSC87251G2D-24IJ 32K EPROM 32K EPROM 24 MHz, Industrial -40 to 85C, window CQPJ 44 24 MHz, Industrial -40 to 85C, window CDIL 40 ROM Description Low Voltage Versions 2.7 to 5.5 V, Industrial TSC87251G2D-L16IC 32K EPROM 16 MHz, Commercial -40 to 85C, window CQPJ 44 13.6 Options (Please consult TEMIC sales) * * * * * ROM code encryption Tape & Real or Dry Pack Known good dice Ceramic packages Extended temperature range: -55C to +125C 13.7 Starter Kit TEMIC Part Number TSC80251-SK Description TSC80251 Starter Kit 13.8 Products Marking ROMless versions TEMIC Temic Part number(1) M C INTEL'97 YYWW . Lot Number Mask ROM versions TEMIC Customer Part number Temic Part number M C INTEL'97 YYWW . Lot Number OTP versions TEMIC Temic Part number(1) M C INTEL'97 YYWW . Lot Number Note: 1. Dry Pack letter (D) not included in the marking. 62 Rev. A - May 7, 1999 Sales Offices Sales Locations Europe Sales Offices A AAAAAAAAAAAAAAAA AAAAAAAAA A AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAA AAAAAAA AAAAAAAAAAAAAAAA AAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAA AAAAAAAAA A AAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAA AAAAAAAAA A A AAAAAAAA A AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAA AAAAAAA AAAAAAA AAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAA AAAAAAA AAAAAAA Finland Germany Italy United Kingdom TEMIC Nordic AB c/o Atmel OY Kappelitie 6B FIN-02200 Tel: 358 9 4520 8219 Fax: 358 9 529 619 TEMIC Semiconductor GmbH Erfurter Strasse 31 85386 Eching Tel: 49 89 3 19 70 0 Fax: 49 89 3 19 46 21 TEMIC Italiana Via Grosio, 10/8 20151 Milano Tel: 39 02 38 03 71 Fax: 39 02 38 03 72 34 TEMIC U.K. Ltd. Easthampstead Road Bracknell, Berkshire RG12 1LX Tel: 44 1344 707 300 Fax: 44 1344 427 371 France TEMIC France Les Quadrants - 3, avenue du centre B.P. 309 78054 St.-Quentin-en-Yvelines Cedex Tel: 33 1 30 60 70 00 Fax: 33 1 30 60 71 11 TEMIC Semiconductor GmbH Kruppstrasse 6 45128 Essen Tel: 49 2 01 24 73 00 Fax: 49 2 01 2 47 30 47 TEMIC Semiconductor GmbH Theresienstrasse 2 74072 Heilbronn Tel: 49 71 31 67 3636 Fax: 49 71 31 67 3163 Spain TEMIC Iberica Principe de Vergara, 112 28002 Madrid Tel: 34 91 564 51 81 Fax: 34 91 562 75 14 Sweden TEMIC Nordic AB Kavallerivaegen 24, Rissne Box 2042 17202 Sundbyberg Tel: 46 8 587 48 800 Fax: 46 8 587 48 850 North America Sales Offices Western Eastern TEMIC North America c/o Atmel Corporation 2325 Orchard Parkway San Jose California 95131 Tel: 1 408 441 0311 Fax: 1 408 436 4200 TEMIC North America Inc. 180 Mount Airy Road, Ste. 100 Basking Ridge New Jersey 07920 Tel: 1 908 630 9200 Fax: 1 908 630 9201 Asia Pacific / Japan Sales Offices China Japan TEMIC Shanghai c/o Atmel Corp 4th floor, Block A Shanghai Eastern Business Bldg 586 Fanyu Road, Shanghai 200052 China Tel: 86 21 6280 9241 Fax: 86 21 6283 8816 Korea Taiwan, R.O.C. TEMIC Semiconductors c/o Atmel Japan K.K. Tonetsushinkawa Bldg. 1-24-8, Shinkawa, chuku Tokyo 104-0033 Tel: 81 3 3523 3551 Fax: 81 3 3523 7581 TEMIC Korea Ltd. Suite 605, Singsong Bldg. 25-4 Yoido-dong Youngdeungpo-Ku 150-010 Seoul Tel: 82 2 785 1136 Fax: 82 2 785 1137 TEMIC Taiwan, c/o Atmel Corp. 9F-1 NO.266 SEC.1 Wen HWA 2RD Lin Kon Hsiang Taipei Hsien Tel: 886 2 2609 5581 Fax: 886 2 2600 2735 Hong Kong Rep. of Singapore TEMIC Hong Kong Ltd. c/o Atmel Asia Ltd # 1216, Chinachem Golden Plaza 77 Mody Road Tsimhatsui East Kowloon, Hong Kong Tel: 852 23 789 789 Fax: 852 23 755 733 TEMIC Singapore Pte Ltd Keppel Building, #03-00 25 Tampines Street 92 Singapore 528877 Tel: 65 260 8223 Fax: 65 787 9819 May 1999 63 This datasheet has been downloaded from: www..com Datasheets for electronic components. |
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